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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 19168 rev: e amendment/ 0 issue date: february 1997 am186 tm em/emlv and am188 tm em/emlv high performance, 80c186-/80c188-compatible and 80l186-/80l188-compatible, 16-bit embedded microcontrollers distinctive characteristics n e86 tm family 80c186- and 80c188-compatible microcontrollers with enhanced bus interface lower system cost with higher performance 3.3-v .3-v operation (am186emlv and am188emlv microcontrollers) n high performance 20-, 25-, 33-, and 40-mhz operating frequencies supports zero-wait-state operation at 25 mhz with 110-ns static memory (am186 tm emlv and am188 tm emlv microcontrollers) and 40 mhz with 70-ns static memory (am186 tm em and am188 tm em microcontrollers) 1-mbyte memory address space 64-kbyte i/o space n new features provide faster access to memory and remove the requirement for a 2x clock input nonmultiplexed address bus phase-locked loop (pll) allows processor to operate at the clock input frequency n new integrated peripherals provide increased functionality while reducing system cost thirty-two programmable i/o (pio) pins asynchronous serial port allows full-duplex, 7-bit or 8-bit data transfers synchronous serial interface allows half-duplex, bidirectional data transfer to and from asics pseudo static ram (psram) controller includes auto refresh capability reset configuration register n familiar 80c186/80l186 peripherals two independent dma channels programmable interrupt controller with six external interrupts three programmable 16-bit timerstimer 1 can be used as a watchdog interrupt timer programmable memory and peripheral chip-select logic programmable wait state generator power-save clock divider n software-compatible with the 80c186/80c188 and 80l186 /80l188 microcontrollers n widely available native development tools, applications, and system software n available in the following packages: 100-pin, thin quad flat pack (tqfp) 100-pin, plastic quad flat pack (pqfp) general description the am186 tm em/emlv and am188 tm em/emlv micro- controllers are the ideal upgrade for 80c186/188 and 80l186/188 microcontroller designs requiring 80c186/ 188 and 80l186/188 microcontroller compatibility, in- creased performance, serial communications, and a di- rect bus interface. the am186em/emlv and am188em/emlv microcontrollers increase the perfor- mance of existing 80c186/188 and 80l186/188 sys- tems while decreasing their cost. the am186em/emlv and am188em/emlv microcon- trollers are part of the amd e86 family of embedded mi- crocontrollers and microprocessors based on the x86 architecture. the e86 family includes the 16- and 32-bit mi- crocontrollers and microprocessors described on page 8 the am186em/emlv and am188em/emlv microcon- trollers integrate the functions of the cpu, nonmulti- plexed address bus, timers, chip selects, interrupt controller, dma controller, psram controller, asynchro- nous serial port, synchronous serial interface, and pro- grammable i/o (pio) pins on one chip. compared to the 80c186/188 and 80l186/188 microcontrollers, the am186em/emlv and am188em/emlv microcontrol- lers enable designers to reduce the size, power con- sumption, and cost of embedded systems, while increasing functionality and performance. the am186em/emlv and am188em/emlv microcon- trollers have been designed to meet the most common requirements of embedded products developed for the office automation, mass storage, communications, and general embedded markets. specific applications in- clude disk drives, hand-held terminals and desktop ter- minals, fax machines, printers, photocopiers, feature phones, cellular phones, pbxs, multiplexers, modems, and industrial controls.
2 am186/188em and am186/188emlv microcontrollers preliminary am186em microcontroller block diagram note: * all pio signals are shared with other physical pins. see the pin descriptions beginning on page 25 and table 2 on page 30 for information on shared functions. control s 2Cs 0 interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers 20-bit source pointers control registers control registers control registers 01 (wdt)2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int4 int3/inta 1/irq int2/inta 0 int1/select int0 tmrout0 tmrout1 drq0 drq1 v cc gnd tmrin0 tmrin1 ardy srdy dt/r den hold hlda asynchronous serial port synchronous serial interface txd rxd sclk sdata sden0 sden1 nmi a19Ca0 ad15Cad0 ale bhe /aden wr wlb whb rd res lcs /once 0 mcs 2Cmcs 0 pcs 6/a2 pcs 3Cpcs 0 pcs 5/a1 ucs /once 1 x2 x1 control registers psram control unit mcs 3/rfsh pio unit pio31C pio0* registers s6/ uzi clkdiv 2
am186/188em and am186/188emlv microcontrollers 3 preliminary am188em microcontroller block diagram note: * all pio signals are shared with other physical pins. see the pin descriptions beginning on page 25 and table 2 on page 30 for information on shared functions. 20-bit source pointers s 2Cs 0 interrupt control unit timer control unit dma unit bus interface unit execution unit chip-select unit clock and power management unit control registers 16-bit count registers max count a registers 16-bit count registers 20-bit destination pointers control registers control registers control registers 01 (wdt)2 0 1 max count b registers refresh control unit control registers control registers control registers clkoutb clkouta int4 int3/inta 1/irq int2/inta 0 int1/select int0 tmrout0 tmrout1 drq0 drq1 v cc gnd tmrin0 tmrin1 ardy srdy dt/r den hold hlda asynchronous serial port synchronous serial interface txd rxd sclk sdata sden0 sden1 nmi s6/ a19Ca0 ad7Cad0 ale wr wb rd res lcs /once 0 mcs 2Cmcs 0 pcs 6/a2 pcs 3Cpcs 0 pcs 5/a1 ucs /once 1 x2 x1 uzi control registers psram control unit mcs 3/rfsh pio unit pio31C pio0* control registers ao15Cao8 rfsh 2/aden clkdiv 2
4 am186/188em and am186/188emlv microcontrollers preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order numbers (valid combinations) are formed by a combination of the elements below. C40 am186em C20 = 20 mhz C25 = 25 mhz C33 = 33 mhz C40 = 40 mhz c temperature range c=emlv commercial (t a =0 c to +70 c) speed option device number/description am186em high-performance, 80c186-compatible, 16-bit embedded microcontroller am188em high-performance, 80c188-compatible, 16-bit embedded microcontroller am186emlv high-performance, 80l186-compatible, low-voltage, 16-bit embedded microcontroller am188emlv high-performance, 80l188-compatible, low-voltage, 16-bit embedded microcontroller \w lead forming \w=trimmed and formed valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combi- nations. notes: 1. the am186em and am188em industrial microcontrollers, as well as the am186emlv and am188emlv commercial microcontrollers, are available in 20- and 25-mhz operating frequencies only. 2. the am186em and am188em industrial microcontrollers are not offered in a low-voltage operating range. 3. the am186em, am188em, am186emlv, and am188emlv microcontrollers are all functionally the same except for their dc characteristics and available frequencies. valid combinations am186emlvC25 valid combinations package type v=100-pin, thin quad flat pack (tqfp) k=100-pin, plastic quad flat pack (pqfp) v am188emlvC25 am188emlvC20 am186emlvC20 vc\w or kc\w am186emC25 am186emC33 am186emC40 am188emC25 am188emC33 am188emC40 vc\w or kc\w am188emC20 am186emC20 ki\w am186emC25 am188emC25 ki\w am188emC20 am186emC20 i=em industrial (t a =C40 c to +85 c) (5-v only) where: t c = case temperature c=em commercial (t c =0 c to +100 c) t a = ambient temperature vc\w or kc\w vc\w or kc\w
am186/188em and am186/188emlv microcontrollers 5 preliminary table of contents distinctive characteristics ............................................................................................................ 1 general description ..................................................................................................................... 1 am186em microcontroller block diagram .................................................................................... 2 am188em microcontroller block diagram .................................................................................... 3 ordering information .................................................................................................................... 4 related amd products ................................................................................................................ 8 key features and benefits ........................................................................................................ 10 tqfp connection diagrams and pinouts .................................................................................. 11 pqfp connection diagrams and pinouts ................................................................................. 17 logic symbolam186em microcontroller ................................................................................ 23 logic symbolam188em microcontroller ................................................................................ 24 pin descriptions pins that are used by emulators ................................................................................... 25 a19Ca0 ........................................................................................................................... 25 ad7Cad0 ....................................................................................................................... 25 ad15Cad8 (am186em microcontroller) ......................................................................... 25 ao15Cao8 (am188em microcontroller) ........................................................................ 25 ale ................................................................................................................................ 25 ardy ............................................................................................................................. 25 bhe /aden (am186em microcontroller only) ............................................................... 26 clkouta ...................................................................................................................... 26 clkoutb ...................................................................................................................... 26 den /pio5 ...................................................................................................................... 26 drq1Cdrq0 .................................................................................................................. 26 dt/r /pio4 ..................................................................................................................... 26 gnd ............................................................................................................................... 27 hlda ............................................................................................................................. 27 hold ............................................................................................................................. 27 int0 ............................................................................................................................... 27 int1/select ................................................................................................................ 27 int2/inta 0/pio31 ......................................................................................................... 27 int3/inta 1/irq ............................................................................................................. 27 int4/pio30 .................................................................................................................... 28 lcs /once 0 ................................................................................................................... 28 mcs 3/rfsh /pio25 ....................................................................................................... 28 mcs 2Cmcs 0 .................................................................................................................. 28 nmi ................................................................................................................................ 28 pcs 3Cpcs 0 ................................................................................................................... 29 pcs 5/a1/pio3 ............................................................................................................... 29 pcs 6/a2/pio2 ............................................................................................................... 29 pio31Cpio0 (shared) .................................................................................................... 29 rd .................................................................................................................................. 31 res ................................................................................................................................ 31 rfsh 2/aden (am188em microcontroller only) ........................................................... 31 rxd/pio28 .................................................................................................................... 31 s 2Cs 0 ............................................................................................................................ 31 s6/clkdiv 2/pio29 ....................................................................................................... 31 sclk/pio20 .................................................................................................................. 32 sdata/pio21 ................................................................................................................ 32 sden1/pio23, sden0/pio22 ....................................................................................... 32 srdy/pio6 .................................................................................................................... 32 tmrin0/pio11 .............................................................................................................. 32
6 am186/188em and am186/188emlv microcontrollers preliminary tmrin1/pio0 ................................................................................................................ 32 tmrout0/pio10 .......................................................................................................... 32 tmrout1/pio1 ............................................................................................................ 32 txd/pio27 ..................................................................................................................... 32 ucs /once 1 .................................................................................................................. 32 uzi /pio26 ...................................................................................................................... 33 v cc ................................................................................................................................. 33 whb (am186em microcontroller only) ......................................................................... 33 wlb (am186em microcontroller only) ........................................................................... 33 wb (am188em microcontroller only) ............................................................................ 33 wr ................................................................................................................................. 33 x1 ................................................................................................................................... 33 x2 ................................................................................................................................... 33 functional description ............................................................................................................... 34 bus operation ............................................................................................................................ 35 bus interface unit ....................................................................................................................... 37 peripheral control block (pcb) ................................................................................................. 38 clock and power management .................................................................................................. 41 chip-select unit.......................................................................................................................... 43 refresh control unit .................................................................................................................. 45 interrupt control unit ................................................................................................................. 45 timer control unit ...................................................................................................................... 46 direct memory access (dma) ................................................................................................... 46 asynchronous serial port .......................................................................................................... 48 synchronous serial interface ..................................................................................................... 48 programmable i/o (pio) pins .................................................................................................... 50 absolute maximum ratings ....................................................................................................... 51 operating ranges ...................................................................................................................... 51 dc characteristics over commercial operating range ........................................................... 51 commercial switching characteristics and waveforms ............................................................ 60
am186/188em and am186/188emlv microcontrollers 7 preliminary list of figures figure 1. example system design ........................................................................................ 10 figure 2. two-component address ...................................................................................... 34 figure 3. am186em microcontroller address busnormal read and write operation ...... 35 figure 4. am186em microcontrollerread and write with address bus disable in effect ..................................................................................................... 36 figure 5. am188em microcontroller address busnormal read and write operation ...... 36 figure 6. am188em microcontrollerread and write with address bus disable in effect ..................................................................................................... 37 figure 7. peripheral control block register map .................................................................. 39 figure 8. am186em and am188em microcontrollers oscillator configurations ................... 41 figure 9. clock organization ................................................................................................ 42 figure 10. dma unit block diagram ....................................................................................... 47 figure 11. synchronous serial interface multiple write .......................................................... 49 figure 12. synchronous serial interface multiple read .......................................................... 49 figure 13. typical i cc versus frequency for the am186emlv and am188emlv ................ 53 figure 14. typical i cc versus frequency for the am186em and am188em ......................... 53 figure 15. thermal resistance( c/watt) ................................................................................ 54 figure 16. thermal characteristics equations ........................................................................ 54 figure 17. typical ambient temperatures for pqfp with 2-layer board ............................... 56 figure 18. typical ambient temperatures for tqfp with 2-layer board ............................... 57 figure 19. typical ambient temperatures for pqfp with 4-layer to 6-layer board ............. 58 figure 20. typical ambient temperatures for tqfp with 4-layer to 6-layer board .............. 59 list of tables table 1. data byte encoding ............................................................................................... 26 table 2. numeric pio pin assignments .............................................................................. 30 table 3. alphabetic pio pin assignments ........................................................................... 30 table 4. bus cycle encoding ............................................................................................... 31 table 5. segment register selection rules ........................................................................ 34 table 6. am186em microcontroller maximum dma transfer rates ................................... 46 table 7. typical power consumption calculation for the am186emlv and am188emlv ............................................................................ 53 table 8. thermal characteristics ( c/watt) ......................................................................... 54 table 9. typical power consumption calculation ............................................................... 55 table 10. junction temperature calculation ......................................................................... 55 table 11. typical ambient temperatures for pqfp with 2-layer board ............................... 56 table 12. typical ambient temperatures for tqfp with 2-layer board ............................... 57 table 13. typical ambient temperatures for pqfp with 4-layer to 6-layer board ............. 58 table 14. typical ambient temperatures for tqfp with 4-layer to 6-layer board .............. 59
8 am186/188em and am186/188emlv microcontrollers preliminary related amd products e86 ? family devices device description 80c186 16-bit microcontroller 80c188 16-bit microcontroller with 8-bit external data bus 80l186 low-voltage, 16-bit microcontroller 80l188 low-voltage, 16-bit microcontroller with 8-bit external data bus am186em high-performance, 80c186-compatible, 16-bit embedded microcontroller am188em high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186emlv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188emlv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186es high-performance, 80c186-compatible, 16-bit embedded microcontroller am188es high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186eslv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188eslv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186er high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller with 32 kbyte of internal ram am188er high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit ex- ternal data bus and 32 kbyte of internal ram lan ? sc300 high-performance, highly integrated, low-voltage, 32-bit embedded microcontroller lansc310 high-performance, single-chip, 32-bit embedded pc/at microcontroller lansc400 single-chip, low-power, pc/at-compatible microcontroller am386 ? dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am386sx high-performance, 32-bit embedded microprocessor with 16-bit external data bus am486 ? dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus at peripheral microcontrollers 186 peripheral microcontrollers lansc400 microcon t roller 80c186 and 80c188 microcontrollers microprocessors lansc300 microcon t roller am386sx/dx microprocessors am486dx microprocessor amd-k5 ? microprocessor time the e86 family of embedded microprocessors and microcontrollers am186es and am188es microcontrollers am186em and am188em microcontrollers am186 and am188 future lansc310 microcon t roller 80l186 and 80l188 microcontrollers am186emlv & am188emlv microcontrollers am186eslv & am188eslv microcontrollers 32-bit future am186er and am188er microcontrollers future k86 ? am486 future
am186/188em and am186/188emlv microcontrollers 9 preliminary related documents the following documents provide additional informa- tion regarding the am186em and am188em microcon- trollers. n the am186em and am188em microcontrollers users manual, order# 19713 n the am186 and am188 family instruction set manual, order# 21267 n the fusione86 sm catalog, order# 19255 third-party development support products the fusione86 program of partnerships for applica- tion solutions provides the customer with an array of products designed to meet critical time-to-market needs. products and solutions available from the amd fusione86 partners include emulators, hardware and software debuggers, board-level products, and soft- ware development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. customer service the amd customer service network includes u.s. of- fices, international offices, and a customer training cen- ter. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff who can answer e86 family hard- ware and software development questions. hotline and world wide web support for answers to technical questions, amd provides a toll-free number for direct access to our corporate ap- plications hotline. also available is the amd world wide web home page and ftp site, which provides the latest e86 family product information, including technical information and data on upcoming product re- leases. corporate applications hotline 800-222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline world wide web home page and ftp site to access the amd home page go to http:// www.amd.com. to download documents and software, ftp to ftp.amd.com and log on as anonymous using your e-mail address as a password. or via your web browser, go to ftp://ftp.amd.com. questions, requests, and input concerning amds www pages can be sent via e-mail to webmaster@amd.com. documentation and literature free e86 family information such as data books, users manuals, data sheets, application notes, the fusione86 partner solutions catalog, and other litera- ture is available with a simple phone call. internation- ally, contact your local amd sales office for complete e86 family literature. literature ordering 800-222-9323 toll-free for u.s. and canada 512-602-5651 direct dial worldwide 800-222-9323 amd facts-on-demand? fax information service, toll-free for u.s. and canada
10 am186/188em and am186/188emlv microcontrollers preliminary key features and benefits the am186em and am188em microcontrollers extend the amd family of microcontrollers based on the indus- try-standard x86 architecture. the am186em and am188em microcontrollers are higher-performance, more integrated versions of the 80c186/188 micropro- cessors, offering a migration path that was previously unavailable. upgrading to the am186em and am188em microcontrollers is an attractive solution for several reasons: n minimized total system cost new peripherals and on-chip system interface logic on the am186em and am188em microcontrollers reduce the cost of existing 80c186/188 designs. n x86 software compatibility 80c186/188-com- patible and upward-compatible with the other mem- bers of the amd e86 family. n enhanced performance the am186em and am188em microcontrollers increase the perfor- mance of 80c186/188 systems, and the demulti- plexed address bus offers faster, unbuffered access to memory. n enhanced functionality the new and enhanced on-chip peripherals of the am186em and am188em microcontrollers include an asynchronous serial port, 32 pios, a watchdog timer, an additional inter- rupt pin, a synchronous serial interface, a psram controller, a 16-bit reset configuration register, and enhanced chip-select functionality. application considerations the integration enhancements of the am186em and am188em microcontrollers provide a high-perfor- mance, low-system-cost solution for 16-bit embedded microcontroller designs. the nonmultiplexed address bus eliminates the need for system-support logic to in- terface memory devices, while the multiplexed ad- dress/data bus maintains the value of previously engineered, customer-specific peripherals and circuits within the upgraded design. figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high per- formance with reduced system cost. clock generation the integrated clock generation circuitry of the am186em and am188em microcontrollers allows the use of a times-one crystal frequency. the design in figure 1 achieves 40-mhz cpu operation while using a 40-mhz crystal. memory interface the integrated memory controller logic of the am186em and am188em microcontrollers provides a direct address bus interface to memory devices. the use of an external address latch controlled by the ad- dress latch enable (ale) signal is no longer needed. individual byte-write-enable signals are provided to eliminate the need for external high/low byte-write-en- able circuitry. the maximum bank size that is program- mable for the memory chip-select signals has been increased to facilitate the use of high-density memory devices. the improved memory timing specifications for the am186em and am188em microcontrollers allow no wait-state operation with 70-ns memory access times at a 40-mhz cpu clock speed. this reduces overall system cost significantly by allowing the use of a more commonly available memory speed and technology. direct memory interface example figure 1 illustrates the am186em microcontroller direct memory interface. the processor a19Ca0 bus con- nects to the memory address inputs, the ad bus con- nects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. the rd output connects to the sram output enable (oe ) pin for read operations. write operations use the byte write enables connected to the sram write enable (we ) pins. the example design uses 2-mbit memory technology (256 kbytes) to fully populate the available address space. two flash prom devices provide 512 kbytes of nonvolatile program storage and two static ram de- vices provide 512 kbytes of data storage area. figure 1 also shows an implementation of an rs-232 console or modem communications port. the rs-232- to-cmos voltage-level converter is required for the electrical interface with the external device. figure 1. example system design x2 x1 rs-232 level converter txd rxd lcs ucs whb wlb we rd we oe cs we ad15 C ad0 a19 C a0 flash prom static ram serial port am186em microcontroller 40-mhz crystal address data we data oe cs address
am186/188em and am186/188emlv microcontrollers 11 preliminary tqfp connection diagrams and pinouts am186em microcontroller top side view100-pin thin quad flat pack (tqfp) note : pin 1 is marked for orientation. gnd 6/a2 5/a1 3 2 ad0 1 ad8 2 ad1 3 ad9 4 ad2 5 ad10 6 ad3 7 ad11 8 ad4 9 ad12 10 ad5 11 12 ad13 13 ad6 14 15 ad14 16 ad7 17 ad15 18 19 20 txd 21 rxd 22 sdata 23 sden1 24 sden0 25 v cc 75 int4 74 73 72 71 70 nmi 69 srdy 68 hold 67 hlda 66 65 64 63 a0 62 a1 61 60 a2 59 a3 58 a4 57 a5 56 a6 55 a7 54 a8 53 a9 52 a10 51 a11 v cc 100 drq0 99 drq1 98 tmrin0 97 tmrout0 96 tmrout1 95 tmrin1 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 int0 78 int1/ 77 int2/ 76 int3/ v cc v cc 1 0 0 1/irq sclk 26 27 28 29 ale 30 ardy 31 32 33 34 35 x1 36 37 38 clkouta 39 40 41 a19 42 a18 43 44 a17 45 a16 46 a15 47 a14 48 a13 49 a12 50 x2 v cc clkoutb v cc /0 /1 2 3/ gnd gnd gnd gnd gnd whb wlb dt/r den mcs 0 mcs 1 bhe/aden wr rd s2 s1 s0 inta inta select ucs once once pcs pcs pcs pcs pcs pcs mcs mcs rfsh res lcs s6/clkdiv 2 uzi am186em microcontroller
12 am186/188em and am186/188emlv microcontrollers preliminary tqfp pin assignmentsam186em microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 ad0 26 sclk/pio20 51 a11 76 int3/inta 1/irq 2 ad8 27 bhe /aden 52 a10 77 int2/inta 0 3 ad1 28 wr 53 a9 78 int1/select 4 ad9 29 rd 54 a8 79 int0 5 ad2 30 ale 55 a7 80 ucs/once 1 6 ad10 31 ardy 56 a6 81 lcs /once 0 7 ad3 32 s 2 57 a5 82 pcs 6/a2/pio2 8 ad11 33 s 1 58 a4 83 pcs 5/a1/pio3 9 ad4 34 s 0 59 a3 84 v cc 10 ad12 35 gnd 60 a2 85 pcs 3/pio19 11 ad5 36 x1 61 v cc 86 pcs 2/pio18 12 gnd 37 x2 62 a1 87 gnd 13 ad13 38 v cc 63 a0 88 pcs 1/pio17 14 ad6 39 clkouta 64 gnd 89 pcs 0/pio16 15 v cc 40 clkoutb 65 whb 90 v cc 16 ad14 41 gnd 66 wlb 91 mcs 2 17 ad7 42 a19/pio9 67 hlda 92 mcs 3/rfsh 18 ad15 43 a18/pio8 68 hold 93 gnd 19 s6/ckldiv 2/pio29 44 v cc 69 srdy/pio6 94 res 20 uzi /pio26 45 a17/pio7 70 nmi 95 tmrin1/pio0 21 txd 46 a16 71 dt/r /pio4 96 tmrout1/pio1 22 rxd 47 a15 72 den /pio5 97 tmrout0/pio10 23 sdata/pio21 48 a14 73 mcs 0/pio14 98 tmrin0/pio11 24 sden1/pio23 49 a13 74 mcs 1/pio15 99 drq1/pio13 25 sden0/pio22 50 a12 75 int4 100 drq0/pio12
am186/188em and am186/188emlv microcontrollers 13 preliminary tqfp pin assignmentsam186em microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 63 ad5 11 gnd 93 s 2 32 a1 62 ad6 14 hlda 67 s6/clkdiv 2/pio29 19 a2 60 ad7 17 hold 68 sclk/pio20 26 a3 59 ad8 2 int0 79 sdata/pio21 23 a4 58 ad9 4 int1/select 78 sden0/pio22 25 a5 57 ad10 6 int2/inta 0 77 sden1/pio23 24 a6 56 ad11 8 int3/inta 1/irq 76 srdy/pio6 69 a7 55 ad12 10 int4 75 tmrin0/pio11 98 a8 54 ad13 13 lcs /once 0 81 tmrin1/pio0 95 a9 53 ad14 16 mcs 0/pio14 73 tmrout0/pio10 97 a10 52 ad15 18 mcs 1/pio15 74 tmrout1/pio1 96 a11 51 ale 30 mcs 2 91 txd 21 a12 50 ardy 31 mcs 3/rfsh 92 ucs /once 1 80 a13 49 bhe /aden 27 nmi 70 uzi /pio26 20 a14 48 clkouta 39 pcs 0/pio16 89 v cc 15 a15 47 clkoutb 40 pcs 1/pio17 88 v cc 38 a16 46 den /pio5 72 pcs 2/pio18 86 v cc 44 a17/pio7 45 drq0/pio12 100 pcs 3/pio19 85 v cc 61 a18/pio8 43 drq1/pio13 99 pcs 5/a1/pio3 83 v cc 84 a19/pio9 42 dt/r/ pio4 71 pcs 6/a2/pio2 82 v cc 90 ad0 1 gnd 12 rd 29 whb 65 ad1 3 gnd 35 res 94 wlb 66 ad2 5 gnd 41 rxd 22 wr 28 ad3 7 gnd 64 s 0 34 x1 36 ad4 9 gnd 87 s 1 33 x2 37
14 am186/188em and am186/188emlv microcontrollers preliminary connection diagram am188em microcontroller top side view100-pin thin quad flat pack (tqfp) note : pin 1 is marked for orientation. gnd 6/a2 5/a1 3 2 ad0 1 ao8 2 ad1 3 ao9 4 ad2 5 ao10 6 ad3 7 ao11 8 ad4 9 ao12 10 ad5 11 12 ao13 13 ad6 14 15 ao14 16 ad7 17 ao15 18 19 20 txd 21 rxd 22 sdata 23 sden1 24 sden0 25 v cc 75 int4 74 73 72 71 70 nmi 69 srdy 68 hold 67 hlda 66 65 64 63 a0 62 a1 61 60 a2 59 a3 58 a4 57 a5 56 a6 55 a7 54 a8 53 a9 52 a10 51 a11 v cc 100 drq0 99 drq1 98 tmrin0 97 tmrout0 96 tmrout1 95 tmrin1 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 int0 78 int1/ 77 int2/ 76 int3/ v cc v cc 1 0 0 1/irq sclk 26 27 28 29 ale 30 ardy 31 32 33 34 35 x1 36 37 38 clkouta 39 40 41 a19 42 a18 43 44 a17 45 a16 46 a15 47 a14 48 a13 49 a12 50 x2 v cc clkoutb v cc /0 /1 2 3/ gnd gnd gnd gnd gnd gnd wb dt/r den mcs 0 mcs 1 rfsh2/aden wr rd s2 s1 s0 inta inta select ucs once once pcs pcs pcs pcs pcs pcs mcs mcs rfsh res lcs s6/clkdiv 2 uzi am188em microcontroller
am186/188em and am186/188emlv microcontrollers 15 preliminary tqfp pin assignmentsam188em microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 ad0 26 sclk/pio20 51 a11 76 int3/inta 1/irq 2 ao8 27 rfsh 2/aden 52 a10 77 int2/inta 0/pio31 3 ad1 28 wr 53 a9 78 int1/select 4 ao9 29 rd 54 a8 79 int0 5 ad2 30 ale 55 a7 80 ucs /once 1 6 ao10 31 ardy 56 a6 81 lcs /once 0 7 ad3 32 s 2 57 a5 82 pcs 6/a2/pio2 8 ao11 33 s 1 58 a4 83 pcs 5/a1/pio3 9 ad4 34 s 0 59 a3 84 v cc 10 ao12 35 gnd 60 a2 85 pcs 3/pio19 11 ad5 36 x1 61 v cc 86 pcs 2/pio18 12 gnd 37 x2 62 a1 87 gnd 13 ao13 38 v cc 63 a0 88 pcs 1/pio17 14 ad6 39 clkouta 64 gnd 89 pcs 0/pio16 15 v cc 40 clkoutb 65 gnd 90 v cc 16 ao14 41 gnd 66 wb 91 mcs 2/pio24 17 ad7 42 a19/pio9 67 hlda 92 mcs 3/rfsh /pio25 18 ao15 43 a18/pio8 68 hold 93 gnd 19 s6/clkdiv 2/pio29 44 v cc 69 srdy/pio6 94 res 20 uzi /pio26 45 a17/pio7 70 nmi 95 tmrin1/pio0 21 txd/pio27 46 a16 71 dt/r/ pio4 96 tmrout1/pio1 22 rxd/pio28 47 a15 72 den /pio5 97 tmrout0/pio10 23 sdata/pio21 48 a14 73 mcs 0/pio14 98 tmrin0/pio11 24 sden1/pio23 49 a13 74 mcs 1/pio15 99 drq1/pio13 25 sden0/pio22 50 a12 75 int4/pio30 100 drq0/pio12
16 am186/188em and am186/188emlv microcontrollers preliminary tqfp pin assignmentsam188em microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 63 ad5 11 gnd 93 s 1 33 a1 62 ad6 14 hlda 67 s 2 32 a2 60 ad7 17 hold 68 s6/c lkdiv 2/pio29 19 a3 59 ale 30 int0 79 sclk/pio20 26 a4 58 ao8 2 int1/select 78 sdata/pio21 23 a5 57 ao9 4 int2/inta 0/pio31 77 sden0/pio22 25 a6 56 ao10 6 int3/inta 1/irq 76 sden1/pio23 24 a7 55 ao11 8 int4/pio30 75 srdy/pio6 69 a8 54 ao12 10 lcs /once 0 81 tmrin0/pio11 98 a9 53 ao13 13 mcs 0/pio14 73 tmrin1/pio0 95 a10 52 ao14 16 mcs 1/pio15 74 tmrout0/pio10 97 a11 51 ao15 18 mcs 2/pio24 91 tmrout1/pio1 96 a12 50 ardy 31 mcs 3/rfsh /pio25 92 txd/pio27 21 a13 49 clkouta 39 nmi 70 ucs /once 1 80 a14 48 clkoutb 40 pcs 0/pio16 89 uzi /pio26 20 a15 47 den /pio5 72 pcs 1/pio17 88 v cc 15 a16 46 drq0/pio12 100 pcs 2/pio18 86 v cc 38 a17/pio7 45 drq1/pio13 99 pcs 3/pio19 85 v cc 44 a18/pio8 43 dt/r /pio4 71 pcs 5/a1/pio3 83 v cc 61 a19/pio9 42 gnd 12 pcs 6/a2/pio2 82 v cc 84 ad0 1 gnd 35 rd 29 v cc 90 ad1 3 gnd 41 res 94 wb 66 ad2 5 gnd 64 rfsh 2/aden 27 wr 28 ad3 7 gnd 65 rxd/pio28 22 x1 36 ad4 9 gnd 87 s 0 34 x2 37
am186/188em and am186/188emlv microcontrollers 17 preliminary pqfp connection diagrams and pinouts am186em microcontroller top side view100-pin plastic quad flat pack (pqfp) note: pin 1 is marked for orientation. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 ad13 ad6 ad14 ad7 ad15 txd rxd sdata sden1 sden0 gnd gnd sclk ale ardy x1 clkouta a19 a18 a17 a16 a15 a14 a12 a13 x2 v cc clkoutb v cc gnd int4 dt/r nmi srdy hold hlda a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 v cc gnd tmrin0 tmrout0 tmrout1 tmrin1 int0 gnd gnd v cc s6/clkdiv drq1 drq0 v cc v cc am186em microcontroller 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 bhe /aden 2 uzi whb wlb den mcs0 wr rd s 2 s 1 s 0 mcs 1 int3/inta 1/irq int2/inta 0 int1/select ucs /once 1 lcs /once 0 pcs 6/a2 pcs 5/a1 pcs 3 pcs 2 pcs 1 pcs 0 mcs 2 mcs 3/rfsh res
18 am186/188em and am186/188emlv microcontrollers preliminary pqfp pin assignmentsam186em microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 sden1/pio23 26 a13 51 mcs 1/pio15 76 drq1/pio13 2 sden0/pio22 27 a12 52 int4/pio30 77 drq0/pio12 3 sclk/pio20 28 a11 53 int3/inta 1/irq 78 ad0 4 bhe /aden 29 a10 54 int2/inta 0/pio31 79 ad8 5 wr 30 a9 55 int1/select 80 ad1 6 rd 31 a8 56 int0 81 ad9 7 ale 32 a7 57 ucs /once 1 82 ad2 8 ardy 33 a6 58 lcs /once 0 83 ad10 9 s 2 34 a5 59 pcs 6/a2/pio2 84 ad3 10 s 1 35 a4 60 pcs 5/a1/pio3 85 ad11 11 s 0 36 a3 61 v cc 86 ad4 12 gnd 37 a2 62 pcs 3/pio19 87 ad12 13 x1 38 v cc 63 pcs 2/pio18 88 ad5 14 x2 39 a1 64 gnd 89 gnd 15 v cc 40 a0 65 pcs 1/pio17 90 ad13 16 clkouta 41 gnd 66 pcs 0/pio16 91 ad6 17 clkoutb 42 whb 67 v cc 92 v cc 18 gnd 43 wlb 68 mcs 2/pio24 93 ad14 19 a19/pio9 44 hlda 69 mcs 3/rfsh /pio25 94 ad7 20 a18/pio8 45 hold 70 gnd 95 ad15 21 v cc 46 srdy/pio6 71 res 96 s6/clkdiv 2/pio29 22 a17/pio7 47 nmi 72 tmrin1/pio0 97 uzi /pio26 23 a16 48 dt/r / pio4 73 tmrout1/pio1 98 txd/pio27 24 a15 49 den /pio5 74 tmrout0/pio10 99 rxd/pio28 25 a14 50 mcs 0/pio14 75 tmrin0/pio11 100 sdata/pio21
am186/188em and am186/188emlv microcontrollers 19 preliminary pqfp pin assignmentsam186em microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 40 ad5 88 gnd 89 s 2 9 a1 39 ad6 91 hlda 44 s6/clkdiv 2/pio29 96 a2 37 ad7 94 hold 45 sclk/pio20 3 a3 36 ad8 79 int0 56 sdata/pio21 100 a4 35 ad9 81 int1/select 55 sden0/pio22 2 a5 34 ad10 83 int2/inta 0/pio31 54 sden1/pio23 1 a6 33 ad11 85 int3/inta 1/irq 53 srdy/pio6 46 a7 32 ad12 87 int4/pio30 52 tmrin0/pio11 75 a8 31 ad13 90 lcs /once 0 58 tmrin1/pio0 72 a9 30 ad14 93 mcs 0/pio14 50 tmrout0/pio10 74 a10 29 ad15 95 mcs 1/pio15 51 tmrout1/pio1 73 a11 28 ale 7 mcs 2/pio24 68 txd/pio27 98 a12 27 ardy 8 mcs 3/rfsh /pio25 69 ucs /once 1 57 a13 26 bhe /aden 4 nmi 47 uzi /pio26 97 a14 25 clkouta 16 pcs 0/pio16 66 v cc 15 a15 24 clkoutb 17 pcs 1/pio17 65 v cc 21 a16 23 den /pio5 49 pcs 2/pio18 63 v cc 38 a17/pio7 22 drq0/pio12 77 pcs 3/pio19 62 v cc 61 a18/pio8 20 drq1/pio13 76 pcs 5/a1/pio3 60 v cc 67 a19/pio9 19 dt/r /pio4 48 pcs 6/a2/pio2 59 v cc 92 ad0 78 gnd 12 rd 6 whb 42 ad1 80 gnd 18 res 71 wlb 43 ad2 82 gnd 41 rxd/pio28 99 wr 5 ad3 84 gnd 64 s 0 11 x1 13 ad4 86 gnd 70 s 1 10 x2 14
20 am186/188em and am186/188emlv microcontrollers preliminary connection diagram am188em microcontroller top side view100-pin plastic quad flat pack (pqfp) note: pin 1 is marked for orientation. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 ad4 ad12 ad5 ad13 ad6 ad14 ad7 ad15 txd rxd sdata sden1 sden0 gnd gnd sclk ale ardy x1 clkouta a19 a18 a17 a16 a15 a14 a12 a13 x2 v cc clkoutb v cc gnd int4 dt/r nmi srdy hold hlda a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 v cc gnd tmrin0 tmrout0 tmrout1 tmrin1 int0 gnd gnd v cc s6/clkdiv drq1 drq0 v cc v cc am188em microcontroller 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 rfsh2/aden 2 uzi gnd wb den mcs0 wr rd s 2 s 1 s 0 mcs 1 int3/inta 1/irq int2/inta 0 int1/select ucs /once 1 lcs /once 0 pcs 6/a2 pcs 5/a1 pcs 3 pcs 2 pcs 1 pcs 0 mcs 2 mcs 3/rfsh res
am186/188em and am186/188emlv microcontrollers 21 preliminary pqfp pin assignmentsam188em microcontroller (sorted by pin number) pin no. name pin no. name pin no. name pin no. name 1 sden1/pio23 26 a13 51 mcs 1/pio15 76 drq1/pio13 2 sden0/pio22 27 a12 52 int4/pio30 77 drq0/pio12 3 sclk/pio20 28 a11 53 int3/inta 1/irq 78 ad0 4 rfsh 2/aden 29 a10 54 int2/inta 0/pio31 79 ao8 5 wr 30 a9 55 int1/select 80 ad1 6 rd 31 a8 56 int0 81 ao9 7 ale 32 a7 57 ucs /once 1 82 ad2 8 ardy 33 a6 58 lcs /once 0 83 ao10 9 s 2 34 a5 59 pcs 6/a2/pio2 84 ad3 10 s 1 35 a4 60 pcs 5/a1/pio3 85 ao11 11 s 0 36 a3 61 v cc 86 ad4 12 gnd 37 a2 62 pcs 3/pio19 87 ao12 13 x1 38 v cc 63 pcs 2/pio18 88 ad5 14 x2 39 a1 64 gnd 89 gnd 15 v cc 40 a0 65 pcs 1/pio17 90 ao13 16 clkouta 41 gnd 66 pcs 0/pio16 91 ad6 17 clkoutb 42 gnd 67 v cc 92 v cc 18 gnd 43 wb 68 mcs 2/pio24 93 ao14 19 a19/pio9 44 hlda 69 mcs 3/rfsh /pio25 94 ad7 20 a18/pio8 45 hold 70 gnd 95 ao15 21 v cc 46 srdy/pio6 71 res 96 s6/clkdiv 2/pio29 22 a17/pio7 47 nmi 72 tmrin1/pio0 97 uzi /pio26 23 a16 48 dt/r / pio4 73 tmrout1/pio1 98 txd/pio27 24 a15 49 den /pio5 74 tmrout0/pio10 99 rxd/pio28 25 a14 50 mcs 0/pio14 75 tmrin0/pio11 100 sdata/pio21
22 am186/188em and am186/188emlv microcontrollers preliminary pqfp pin assignmentsam188em microcontroller (sorted by pin name) pin name no. pin name no. pin name no. pin name no. a0 40 ad5 88 gnd 89 s 1 10 a1 39 ad6 91 hlda 44 s 2 9 a2 37 ad7 94 hold 45 s6/clkdiv 2/pio29 96 a3 36 ale 7 int0 56 sclk/pio20 3 a4 35 ao8 79 int1/select 55 sdata/pio21 100 a5 34 ao9 81 int2/inta 0/pio31 54 sden0/pio22 2 a6 33 ao10 83 int3/inta 1/irq 53 sden1/pio23 1 a7 32 ao11 85 int4/pio30 52 srdy/pio6 46 a8 31 ao12 87 lcs /once 0 58 tmrin0/pio11 75 a9 30 ao13 90 mcs 0/pio14 50 tmrin1/pio0 72 a10 29 ao14 93 mcs 1/pio15 51 tmrout0/pio10 74 a11 28 ao15 95 mcs 2/pio24 68 tmrout1/pio1 73 a12 27 ardy 8 mcs 3/rfsh /pio25 69 txd/pio27 98 a13 26 clkouta 16 nmi 47 ucs /once 1 57 a14 25 clkoutb 17 pcs 0/pio16 66 uzi /pio26 97 a15 24 den /pio5 49 pcs 1/pio17 65 v cc 15 a16 23 drq0/pio12 77 pcs 2/pio18 63 v cc 21 a17/pio7 22 drq1/pio13 76 pcs 3/pio19 62 v cc 38 a18/pio8 20 dt/r /pio4 48 pcs 5/a1/pio3 60 v cc 61 a19/pio9 19 gnd 12 pcs 6/a2/pio2 59 v cc 67 ad0 78 gnd 18 rd 6 v cc 92 ad1 80 gnd 41 res 71 wb 43 ad2 82 gnd 42 rfsh 2/aden 4 wr 5 ad3 84 gnd 64 rxd/pio28 99 x1 13 ad4 86 gnd 70 s 0 11 x2 14
am186/188em and am186/188emlv microcontrollers 23 preliminary logic symbolam186em microcontroller notes: * these signals are the normal function of a pin that can be used as a pio. see the pin descriptions beginning on page 25 and table 2 on page 30 for information on shared function. ** all pio signals are shared with other physical pins. x1 x2 clkouta clkoutb a19Ca0 ad15Cad0 ale whb wlb rd wr s 2Cs 0 hold hlda dt/r den ardy srdy tmrin0 tmrout0 sden1Csden0 sclk sdata 20 16 clocks address and address/data buses bus control timer control synchronous serial port control res int4 int3 / inta 1/irq int2 / inta 0 int1 / select int0 nmi pcs 6/a2 pcs 5/a1 pcs 3Cpcs 0 lcs /once 0 mcs 2Cmcs 0 ucs /once 1 drq1Cdrq0 txd rxd pio32Cpio0 4 reset control and interrupt service memory and peripheral control dma control asynchronous serial port control programmable i/o control 2 3 tmrin1 tmrout1 3 2 mcs 3/rfsh s6/clkdiv 2 bhe /aden uzi ** * * * * * * * * * * * * * * * * * * * * * * * 32 shared
24 am186/188em and am186/188emlv microcontrollers preliminary logic symbolam188em microcontroller notes: * these signals are the normal function of a pin that can be used as a pio. see the pin descriptions beginning on page 25 and table 2 on page 30 for information on shared function. ** all pio signals are shared with other physical pins. x1 x2 clkouta clkoutb ao15Cao8 ad7Cad0 s6/clkdiv 2 ale rfsh 2/aden rd wr s 2Cs 0 hold hlda dt/r den ardy srdy tmrin0 tmrout0 sden1Csden0 sclk sdata 8 8 clocks address and address/data buses bus control timer control synchronous serial port control res int4 int3 / inta 1/irq int2 / inta 0 int1 / select int0 nmi pcs 6/a2 pcs 5/a1 pcs 3Cpcs 0 lcs /once 0 mcs 2Cmcs 0 ucs /once 1 drq1 C drq0 txd rxd pio31Cpio0 4 32 shared reset control and interrupt service memory and peripheral control dma control asynchronous serial port control programmable i/o control 2 3 uzi tmrin1 tmrout1 3 2 mcs 3/rfsh a19Ca0 20 wb ** * * * * * * * * * * * * * * * * * * * * * * *
am186/188em and am186/188emlv microcontrollers 25 preliminary pin descriptions pins that are used by emulators the following pins are used by emulators: a19Ca0, ao15Cao8, ad7Cad0, ale, bhe /aden (on the am186em), clkouta, rfsh 2/aden (on the am188em), rd , s 2Cs 0, s6/clkdiv 2, and uzi . emulators require that s6/clkdiv 2 and uzi be config- ured in their normal functionality, that is as s6 and uzi . if bhe /aden (on the 186) or rfsh 2/aden (on the 188) is held low during the rising edge of res , s6 and uzi are configured in their normal functionality. pin terminology the following terms are used to describe the pins: input an input-only pin. output an output-only pin. input/output a pin that can be either input or output. synchronous synchronous inputs must meet setup and hold times in relation to clkouta. synchronous outputs are synchronous to clkouta. asynchronous inputs or outputs that are asynchronous to clkouta. a19Ca0 (a19/pio9, a18/pio8, a17/pio7) address bus (output, three-state, synchronous) these pins supply nonmultiplexed memory or i/o ad- dresses to the system one-half of a clkouta period earlier than the multiplexed address and data bus (ad15Cad0 on the 186 or ao15Cao8 and ad7Cad0 on the 188). during a bus hold or reset condition, the address bus is in a high-impedance state. ad7 C ad0 address and data bus (input/output, three-state, synchronous, level-sensitive) these time-multiplexed pins supply partial memory or i/o addresses, as well as data, to the system. this bus supplies the low-order 8 bits of an address to the sys- tem during the first period of a bus cycle (t 1 ), and it sup- plies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when wlb is negated, these pins are three-stated during t 2 , t 3 , and t 4 . during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the 186, ao15Cao8 and ad7C ad0 for the 188) can also be used to load system con- figuration information into the internal reset configura- tion register. ad15 C ad8 (am186em microcontroller) ao15 C ao8 (am188em microcontroller) address and data bus (input/output, three-state, synchronous, level-sensitive) address-only bus (output, three-state, synchronous, level-sensitive) ad15Cad8 on the am186em microcontroller, these time-multiplexed pins supply memory or i/o addresses and data to the system. this bus can supply an ad- dress to the system during the first period of a bus cycle (t 1 ). it supplies data to the system during the remaining periods of that cycle (t 2 , t 3 , and t 4 ). the address phase of these pins can be disabled. see the aden description with the bhe /aden pin. when whb is negated, these pins are three-stated during t 2 , t 3 , and t 4. during a bus hold or reset condition, the address and data bus is in a high-impedance state. during a power-on reset, the address and data bus pins (ad15Cad0 for the 186, ao15Cao8 and ad7C ad0 for the 188) can also be used to load system con- figuration information into the internal reset configura- tion register. ao15 Cao8 on the am188em microcontroller, the address-only bus (ao15Cao8) contains valid high- order address bits from bus cycles t 1 Ct 4 . these outputs are floated during a bus hold or reset. on the am188em microcontroller, ao15Cao8 com- bine with ad7Cad0 to form a complete multiplexed ad- dress bus while ad7Cad0 is the 8-bit data bus. ale address latch enable (output, synchronous) this pin indicates to the system that an address ap- pears on the address and data bus (ad15Cad0 for the 186 or ao15Cao8 and ad7Cad0 for the 188). the ad- dress is guaranteed valid on the trailing edge of ale. this pin is three-stated during once mode. this pin is not three-stated during a bus hold or reset. ardy asynchronous ready (input, asynchronous, level-sensitive) this pin indicates to the microcontroller that the ad- dressed memory space or i/o device will complete a data transfer. the ardy pin accepts a rising edge that is asynchronous to clkouta and is active high. the
26 am186/188em and am186/188emlv microcontrollers preliminary falling edge of ardy must be synchronized to clk- outa. to always assert the ready condition to the mi- crocontroller, tie ardy high. if the system does not use ardy, tie the pin low to yield control to srdy. bhe /aden (am186em microcontroller only) bus high enable (three-state, output, synchronous) address enable (input, internal pullup) bhe during a memory access, this pin and the least- significant address bit (ad0 or a0) indicate to the sys- tem which bytes of the data bus (upper, lower, or both) participate in a bus cycle. the bhe /aden and ad0 pins are encoded as shown in table 1. bhe is asserted during t 1 and remains asserted through t 3 and t w . bhe does not need to be latched. bhe floats during bus hold and reset. on the am186em and am188em microcontrollers, wlb and whb implement the functionality of bhe and ad0 for high and low byte write enables. table 1. data byte encoding bhe /aden also signals dram refresh cycles when using the multiplexed address and data (ad) bus. a re- fresh cycle is indicated when both bhe /aden and ad0 are high. during refresh cycles, the a bus and the ad bus are not guaranteed to provide the same address during the address phase of the ad bus cycle. for this reason, the a0 signal cannot be used in place of the ad0 signal to determine refresh cycles. psram re- freshes also provide an additional rfsh signal (see the mcs 3/rfsh pin description on page 28). aden if bhe /aden is held high or left floating dur- ing power-on reset, the address portion of the ad bus (ad15Cad0 for the 186 or ao15Cao8 and ad7Cad0 for the 188) is enabled or disabled during lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. if the da bit is set, the memory ad- dress is accessed on the a19Ca0 pins. there is a weak internal pullup resistor on bhe /aden so no external pullup is required. this mode of operation reduces power consumption. if bhe /aden is held low on power-on reset, the ad bus drives both addresses and data, regardless of the da bit setting. this pin is sampled on the rising edge of res . (s6 and uzi also assume their normal functional- ity in this instance. see table 2 on page 30.) note: on the am188em microcontroller, ao15 C ao8 are driven during the entire bus cycle, regardless of the setting of the da bit in the umcs and lmcs registers. clkouta clock output a (output, synchronous) this pin supplies the internal clock to the system. de- pending on the value of the power-save control register (pdcon), clkouta operates at either the crystal input frequency (x1), the power-save frequency, or is three-stated. clkouta remains active during reset and bus hold conditions. clkoutb clock output b (output, synchronous) this pin supplies an additional clock to the system. de- pending upon the value of the power-save control reg- ister (pdcon), clkoutb operates at either the crystal input frequency (x1), the power-save fre- quency, or is three-stated. clkoutb remains active during reset and bus hold conditions. den /pio5 data enable (output, three-state, synchronous) this pin supplies an output enable to an external data- bus transceiver. den is asserted during memory, i/o, and interrupt acknowledge cycles. den is deasserted when dt/r changes state. den floats during a bus hold or reset condition. drq1 C drq0 (drq1/pio13, drq0/pio12) dma requests (input, synchronous, level-sensitive) these pins indicate to the microcontroller that an exter- nal device is ready for dma channel 1 or channel 0 to perform a transfer. drq1Cdrq0 are level-triggered and internally synchronized. the drq signals are not latched and must remain ac- tive until serviced. dt/r /pio4 data transmit or receive (output, three-state, synchronous) this pin indicates which direction data should flow through an external data-bus transceiver. when dt/r is asserted high, the microcontroller transmits data. when this pin is deasserted low, the microcontroller receives data. dt/r floats during a bus hold or reset condition. bhe ad0 type of bus cycle 0 0 word transfer 0 1 high byte transfer (bits 15 C 8) 1 0 low byte transfer (bits 7 C 0) 1 1 refresh
am186/188em and am186/188emlv microcontrollers 27 preliminary gnd ground the ground pins connect the system ground to the mi- crocontroller. hlda bus hold acknowledge (output, synchronous) this pin is asserted high to indicate to an external bus master that the microcontroller has released control of the local bus. when an external bus master requests control of the local bus (by asserting hold), the micro- controller completes the bus cycle in progress and then relinquishes control of the bus to the external bus mas- ter by asserting hlda and floating den , rd , wr , s 2C s 0, ad15Cad0, s6, a19Ca0, bhe , whb , wlb , and dt/r , and then driving the chip selects ucs , lcs , mcs 3Cmcs 0, pcs 6Cpcs 5, and pcs 3Cpcs 0 high. when the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting hold. the microcontroller responds by deasserting hlda. if the microcontroller requires access to the bus (i.e. for refresh), it will deassert hlda before the external bus master deasserts hold. the external bus master must be able to deassert hold and allow the micro- controller access to the bus. see the timing diagrams for bus hold on page 92. hold bus hold request (input, synchronous, level-sensitive) this pin indicates to the microcontroller that an external bus master needs control of the local bus. the am186em and am188em microcontrollers hold latency time is a function of the activity occurring in the processor when the hold request is received. a dram request will delay a hold request when both requests are made at the same time. in addition, if locked transfers are performed, the hold latency time is increased by the length of the locked transfer. for more information, see the hlda pin description. int0 maskable interrupt request 0 (input, asynchronous) this pin indicates to the microcontroller that an inter- rupt request has occurred. if the int0 pin is not masked, the microcontroller transfers program execu- tion to the location specified by the int0 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int0 until the request is acknowledged. int1/select maskable interrupt request 1 (input, asynchronous) slave select (input, asynchronous) int1 this pin indicates to the microcontroller that an interrupt request has occurred. if int1 is not masked, the microcontroller transfers program execution to the location specified by the int1 vector in the microcon- troller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int1 until the request is acknowledged. select when the microcontroller interrupt control unit is operating as a slave to an external interrupt con- troller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. the int0 pin must indicate to the microcontroller that an interrupt has occurred before the select pin indi- cates to the microcontroller that the interrupt type ap- pears on the bus. int2/inta 0/pio31 maskable interrupt request 2 (input, asynchronous) interrupt acknowledge 0 (output, synchronous) int2 this pin indicates to the microcontroller that an interrupt request has occurred. if the int2 pin is not masked, the microcontroller transfers program execu- tion to the location specified by the int2 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int2 until the request is acknowledged. int2 becomes inta 0 when int0 is configured in cas- cade mode. inta0 when the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on int0. the periph- eral issuing the interrupt request must provide the mi- crocontroller with the corresponding interrupt type. int3/inta 1/irq maskable interrupt request 3 (input, asynchronous) interrupt acknowledge 1 (output, synchronous) slave interrupt request (output, synchronous) int3 this pin indicates to the microcontroller that an interrupt request has occurred. if the int3 pin is not masked, the microcontroller then transfers program ex- ecution to the location specified by the int3 vector in the microcontroller interrupt vector table.
28 am186/188em and am186/188emlv microcontrollers preliminary interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int3 until the request is acknowledged. int3 becomes inta 1 when int1 is configured in cas- cade mode. inta 1 when the microcontroller interrupt control unit is operating in cascade mode or special fully-nested mode, this pin indicates to the system that the micro- controller needs an interrupt type to process the inter- rupt request on int1. in both modes, the peripheral issuing the interrupt request must provide the micro- controller with the corresponding interrupt type. irq when the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an in- terrupt request to the external master interrupt control- ler. int4/pio30 maskable interrupt request 4 (input, asynchronous) this pin indicates to the microcontroller that an inter- rupt request has occurred. if the int4 pin is not masked, the microcontroller then transfers program ex- ecution to the location specified by the int4 vector in the microcontroller interrupt vector table. interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. to guarantee in- terrupt recognition, the requesting device must con- tinue asserting int4 until the request is acknowledged. lcs /once 0 lower memory chip select (output, synchronous, internal pullup) once mode request 0 (input) lcs this pin indicates to the system that a memory access is in progress to the lower memory block. the base address and size of the lower memory block are programmable up to 512 kbytes. lcs is held high dur- ing a bus hold condition. once 0 during reset this pin and once 1 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode; otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. to guarantee that the microcontroller does not inadvertently enter once mode, once 0 has a weak in- ternal pullup resistor that is active only during reset. this pin is not three-stated during a bus hold condition. mcs 3/rfsh /pio25 midrange memory chip select 3 (output, synchronous, internal pullup) automatic refresh (output, synchronous) mcs 3 this pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 3 is held high during a bus hold condition. in addition, this pin has a weak internal pullup resistor that is active during reset. rfsh this pin provides a signal timed for auto re- fresh to psram devices. it is only enabled to function as a refresh pulse when the psram mode bit is set in the lmcs register. an active low pulse is generated for 1.5 clock cycles with an adequate deassertion pe- riod to ensure that overall auto refresh cycle time is met. this pin is not three-stated during a bus hold condi- tion. mcs 2 C mcs 0 (mcs 2/pio24, mcs 1/pio15, mcs 0/pio14) midrange memory chip selects (output, synchronous, internal pullup) these pins indicate to the system that a memory ac- cess is in progress to the corresponding region of the midrange memory block. the base address and size of the midrange memory block are programmable. mcs 2Cmcs 0 are held high during a bus hold condi- tion. in addition, they have weak internal pullup resis- tors that are active during reset. nmi nonmaskable interrupt (input, synchronous, edge- sensitive) this pin indicates to the microcontroller that an inter- rupt request has occurred. the nmi signal is the high- est priority hardware interrupt and, unlike the int4C int0 pins, cannot be masked. the microcontroller al- ways transfers program execution to the location spec- ified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when nmi is as- serted. although nmi is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. there is no bit associated with nmi in the interrupt in-service or interrupt request reg- isters. this means that a new nmi request can interrupt an executing nmi interrupt service routine. as with all hardware interrupts, the if (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. however, if maskable in- terrupts are re-enabled by software in the nmi interrupt service routine, via the sti instruction for example, the fact that an nmi is currently in service will not have any
am186/188em and am186/188emlv microcontrollers 29 preliminary effect on the priority resolution of maskable interrupt re- quests. for this reason, it is strongly advised that the interrupt service routine for nmi does not enable the maskable interrupts. an nmi transition from low to high is latched and syn- chronized internally, and it initiates the interrupt at the next instruction boundary. to guarantee that the inter- rupt is recognized, the nmi pin must be asserted for at least one clkouta period. pcs 3 C pcs 0 (pcs 3/pio19, pcs 2/pio18, pcs 1/pio17, pcs 0/pio16) peripheral chip selects (output, synchronous) these pins indicate to the system that a memory ac- cess is in progress to the corresponding region of the peripheral memory block (either i/o or memory ad- dress space). the base address of the peripheral memory block is programmable. pcs 3 Cpcs 0 are held high during a bus hold condition. they are also held high during reset. pcs 4 is not available on the am186em and am188em microcontrollers. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range cov- ered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. pcs 5/a1/pio3 peripheral chip select 5 (output, synchronous) latched address bit 1 (output, synchronous) pcs 5 this pin indicates to the system that a memory access is in progress to the sixth region of the periph- eral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 5 is held high during a bus hold condition. it is also held high during reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. a1 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched ad- dress bit 1 to the system. during a bus hold condition, a1 retains its previously latched value. pcs 6/a2/pio2 peripheral chip select 6 (output, synchronous) latched address bit 2 (output, synchronous) pcs 6 this pin indicates to the system that a memory access is in progress to the seventh region of the pe- ripheral memory block (either i/o or memory address space). the base address of the peripheral memory block is programmable. pcs 6 is held high during a bus hold condition or reset. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256- byte address range, which is twice the address range covered by peripheral chip selects in the 80c186 and 80c188 microcontrollers. a2 when the ex bit in the mcs and pcs auxiliary register is 0, this pin supplies an internally latched ad- dress bit 2 to the system. during a bus hold condition, a2 retains its previously latched value. pio31 C pio0 (shared) programmable i/o pins (input/output, asynchronous, open-drain) the am186em and am188em microcontrollers pro- vide 32 individually programmable i/o pins. each pio can be programmed with the following attributes: pio function (enabled/disabled), direction (input/output), and weak pullup or pulldown. the pins that are multiplexed with pio31Cpio0 are listed in table 2 and table 3. after power-on reset, the pio pins default to various configurations. the column titled power-on reset sta- tus in table 2 and table 3 lists the defaults for the pios. the system initialization code must reconfigure any pios as required. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset.
30 am186/188em and am186/188emlv microcontrollers preliminary table 2. numeric pio pin assignments notes: 1. these pins are used by emulators. (emulators also use s 2 Cs 0 , res , nmi , clkouta , bhe , ale , ad15Cad0 , and a16 C a0. ) 2. these pins revert to normal operation if bhe /aden (186) or rfsh 2/aden (188) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. table 3. alphabetic pio pin assignments notes: 1. these pins are used by emulators. (emulators also use s 2 Cs 0 , res , nmi , clkouta , bhe , ale , ad15Cad0 , and a16 C a0. ) 2. these pins revert to normal operation if bhe /aden (186) or rfsh 2/aden (188) is held low during power-on reset. 3. when used as a pio, input with pullup option available. 4. when used as a pio, input with pulldown option available. pio no associated pin power-on reset status 0 tmrin1 input with pullup 1 tmrout1 input with pulldown 2 pcs 6/a2 input with pullup 3 pcs 5/a1 input with pullup 4 dt/r normal operation (3) 5 den normal operation (3) 6 srdy normal operation (4) 7 (1) a17 normal operation (3) 8 (1) a18 normal operation (3) 9 (1) a19 normal operation (3) 10 tmrout0 input with pulldown 11 tmrin0 input with pullup 12 drq0 input with pullup 13 drq1 input with pullup 14 mcs 0 input with pullup 15 mcs 1 input with pullup 16 pcs 0 input with pullup 17 pcs 1 input with pullup 18 pcs 2 input with pullup 19 pcs 3 input with pullup 20 sclk input with pullup 21 sdata input with pullup 22 sden0 input with pulldown 23 sden1 input with pulldown 24 mcs 2 input with pullup 25 mcs 3/rfsh input with pullup 26 (1,2) uzi input with pullup 27 txd input with pullup 28 rxd input with pullup 29 (1,2) s6/clkdiv 2 input with pullup 30 int4 input with pullup 31 int2 input with pullup associated pin pio no power-on reset status a17 (1) 7 normal operation (3) a18 (1) 8 normal operation (3) a19 (1) 9 normal operation (3) den 5 normal operation (3) drq0 12 input with pullup drq1 13 input with pullup dt/r 4 normal operation (3) int2 31 input with pullup int4 30 input with pullup mcs 0 14 input with pullup mcs 1 15 input with pullup mcs 2 24 input with pullup mcs 3/rfsh 25 input with pullup pcs 0 16 input with pullup pcs 1 17 input with pullup pcs 2 18 input with pullup pcs 3 19 input with pullup pcs 5/a1 3 input with pullup pcs 6/a2 2 input with pullup rxd 28 input with pullup s6/clkdiv 2 (1,2) 29 input with pullup sclk 20 input with pullup sdata 21 input with pullup sden0 22 input with pulldown sden1 23 input with pulldown srdy 6 normal operation (4) tmrin0 11 input with pullup tmrin1 0 input with pullup tmrout0 10 input with pulldown tmrout1 1 input with pulldown txd 27 input with pullup uzi (1,2) 26 input with pullup
am186/188em and am186/188emlv microcontrollers 31 preliminary rd read strobe (output, synchronous, three-state) this pin indicates to the system that the microcontroller is performing a memory or i/o read cycle. rd is guar- anteed not to be asserted before the address and data bus is floated during the address-to-data transition. rd floats during a bus hold condition. res reset (input, asynchronous, level-sensitive) this pin requires the microcontroller to perform a reset. when res is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and cpu control is transferred to the reset address ffff0h. res must be held low for at least 1 ms. res can be asserted asynchronously to clkouta because res is synchronized internally. for proper ini- tialization, v cc must be within specifications, and clk- outa must be stable for more than four clkouta periods during which res is asserted. the microcontroller begins fetching instructions ap- proximately 6.5 clkouta periods after res is deas- serted. this input is provided with a schmitt trigger to facilitate power-on res generation via an rc network. rfsh 2/aden (am188em microcontroller only) refresh 2 (three-state, output, synchronous) address enable (input, internal pullup) rfsh 2 asserted low to signify a dram refresh bus cycle. the use of rfsh 2/aden to signal a refresh is not valid when psram mode is selected. instead, the mcs 3/rfsh signal is provided to the psram. aden if rfsh 2/aden is held high or left floating on power-on reset, the ad bus (ao15Cao8 and ad7C ad0) is enabled or disabled during the address portion of lcs and ucs bus cycles based on the da bit in the lmcs and umcs registers. if the da bit is set, the memory address is accessed on the a19Ca0 pins. this mode of operation reduces power consumption. for more information, see the bus operation section on page 37. there is a weak internal pullup resistor on rfsh 2/aden so no external pullup is required. if rfsh 2/aden is held low on power-on reset, the ad bus drives both addresses and data regardless of the da bit setting. the pin is sampled one crystal clock cycle after the rising edge of res . rfsh 2/aden is three-stated during bus holds and once mode. rxd/pio28 receive data (input, asynchronous) this pin supplies asynchronous serial receive data from the system to the internal uart of the microcon- troller. s 2 C s 0 bus cycle status (output, three-state, synchronous) these pins indicate to the system the type of bus cycle in progress. s 2 can be used as a logical memory or i/o indicator, and s 1 can be used as a data transmit or receive indicator. s 2 Cs 0 float during bus hold and hold acknowl- edge conditions. the s 2Cs 0 pins are encoded as shown in table 4. table 4. bus cycle encoding s6/clkdiv 2/pio29 bus cycle status bit 6 (output, synchronous) clock divide by 2 (input, internal pullup) s6 during the second and remaining periods of a cycle (t 2 , t 3 , and t 4 ), this pin is asserted high to indicate a dma-initiated bus cycle. during a bus hold or reset condition, s6 floats. clkdiv 2 if s6/clkdiv 2/pio29 is held low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. if this mode is selected, the pll is disabled. the pin is sampled on the rising edge of res . if s6 is to be used as pio29 in input mode, the device driving pio29 must not drive the pin low during power- on reset. s6/clkdiv 2/pio29 defaults to a pio input with pullup, so the pin does not need to be driven high exter- nally. s 2 s 1 s 0 bus cycle 0 0 0 interrupt acknowledge 0 0 1 read data from i/o 0 1 0 write data to i/o 0 1 1 halt 1 0 0 instruction fetch 1 0 1 read data from memory 1 1 0 write data to memory 1 1 1 none (passive)
32 am186/188em and am186/188emlv microcontrollers preliminary sclk/pio20 serial clock (output, synchronous) this pin supplies the synchronous serial interface (ssi) clock to a slave device, allowing transmit and receive operations to be synchronized between the microcon- troller and the slave. sclk is derived from the micro- controller internal clock and then divided by 2, 4, 8, or 16 depending on register settings. an access to any of the ssr or ssd registers activates sclk for eight sclk cycles (see figure 11 and figure 12 on page 49). when sclk is inactive, it is held high by the microcontroller. sdata/pio21 serial data (input/output, synchronous) this pin transmits synchronous serial interface (ssi) data to and from a slave device. when sdata is inac- tive, a weak keeper holds the last value of sdata on the pin. sden1/pio23, sden0/pio22 serial data enables (output, synchronous) these pins enable data transfers on port 1 and port 0 of the synchronous serial interface (ssi). the micro- controller asserts either sden1 or sden0 at the be- ginning of a transfer and deasserts it after the transfer is complete. when sden1Csden0 are inactive, they are held low by the microcontroller. srdy/pio6 synchronous ready (input, synchronous, level-sensitive) this pin indicates to the microcontroller that the ad- dressed memory space or i/o device will complete a data transfer. the srdy pin accepts an active high input synchronized to clkouta. using srdy instead of ardy allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ardy. to al- ways assert the ready condition to the microcontroller, tie srdy high. if the system does not use srdy, tie the pin low to yield control to ardy. tmrin0/pio11 timer input 0 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 0. after internally synchronizing a low-to-high transition on tmrin0, the microcontroller increments the timer. tmrin0 must be tied high if not being used. tmrin1/pio0 timer input 1 (input, synchronous, edge-sensitive) this pin supplies a clock or control signal to the internal microcontroller timer 1. after internally synchronizing a low-to-high transition on tmrin1, the microcontroller increments the timer. tmrin1 must be tied high if not being used. tmrout0/pio10 timer output 0 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. tmrout0 is floated during a bus hold or reset. tmrout1/pio1 timer output 1 (output, synchronous) this pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. tmrout1 can also be programmed as a watch- dog timer. tmrout1 is floated during a bus hold or re- set. txd/pio27 transmit data (output, asynchronous) this pin supplies asynchronous serial transmit data to the system from the internal uart of the microcontrol- ler. ucs /once 1 upper memory chip select (output, synchronous) once mode request 1 (input, internal pullup) ucs this pin indicates to the system that a memory access is in progress to the upper memory block. the base address and size of the upper memory block are programmable up to 512 kbytes. ucs is held high dur- ing a bus hold condition. after power-on reset, ucs is asserted because the pro- cessor begins executing at ffff0h and the default config- uration for the ucs chip select is 64 kbytes from f0000h to fffffh. once 1 during reset, this pin and once 0 indicate to the microcontroller the mode in which it should operate. once 0 and once 1 are sampled on the rising edge of res . if both pins are asserted low, the microcontroller enters once mode. otherwise, it operates normally. in once mode, all pins assume a high-impedance state and remain in that state until a subsequent reset oc- curs. to guarantee that the microcontroller does not in- advertently enter once mode, once 1 has a weak internal pullup resistor that is active only during a reset. this pin is not three-stated during a bus hold condition.
am186/188em and am186/188emlv microcontrollers 33 preliminary uzi /pio26 upper zero indicate (output, synchronous) uzi this pin lets the designer determine if an access to the interrupt vector table is in progress by oring it with bits 15C10 of the address and data bus (ad15C ad10 on the 186 and ao15Cao10 on the 188). uzi is the logical or of the inverted a19Ca16 bits, and it as- serts in the first period of a bus cycle and is held throughout the cycle. this signal should be pulled high or allowed to float at reset. if this pin is low at the negation of reset, the am186em and am188em microcontrollers will enter a re- served clock test mode. v cc power supply (input) these pins supply power (+5 v) to the microcontroller. whb (am186em microcontroller only) write high byte (output, three-state, synchronous) this pin and wlb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are eliminated. whb is asserted with ad15Cad8. whb is the logical or of bhe and wr . this pin floats during reset. wlb (am186em microcontroller only) wb (am188em microcontroller only) write low byte (output, three-state, synchronous) write byte (output, three-state, synchronous) wlb this pin and whb indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. in 80c186 designs, this information is provided by bhe , ad0, and wr . however, by using whb and wlb , the standard system interface logic and external address latch that were required are elim- inated. wlb is asserted with ad7Cad0. wlb is the logical or of ad0 and wr . this pin floats during reset. wb on the am188em microcontroller, this pin indi- cates a write to the bus. wb uses the same early timing as the nonmultiplexed address bus. wb is associated with ad7Cad0. this pin floats during reset. wr write strobe (output, synchronous) this pin indicates to the system that the data on the bus is to be written to a memory or i/o device. wr floats during a bus hold or reset condition. x1 crystal input (input) this pin and the x2 pin provide connections for a fun- damental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, con- nect the source to the x1 pin and leave the x2 pin un- connected. x2 crystal output (output) this pin and the x1 pin provide connections for a fun- damental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. to provide the microcontroller with an external clock source, leave the x2 pin unconnected and connect the source to the x1 pin.
34 am186/188em and am186/188emlv microcontrollers preliminary functional description amds am186 and am188 family of microcontrollers and microprocessors is based on the architecture of the original 8086 and 8088 microcontrollers and cur- rently includes the 80c186, 80c188, 80l186, 80l188, am186em, am188em, am186emlv, am188emlv, am186es, am188es, am186eslv, am188eslv, am186er, and am188er microcontrollers. all family members contain the same basic set of registers, instructions, and addressing modes and are compatible with the industry-standard 80c186/188 microcontrollers. a full description of all the am186em and am188em microcontroller registers is included in the am186em and am188em microcontrollers users manual , order# 19713. the instruction set for the am186em and am188em microcontrollers is documented in the am186 and am188 family instruction set manual , order# 21267. memory organization memory is organized in sets of segments. each seg- ment is a linear contiguous sequence of 64k (2 16 ) 8-bit bytes. memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. the 16-bit segment values are contained in one of four internal segment registers (cs, ds, ss, or es). the physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see figure 3). this allows for a 1-mbyte physical address size. all instructions that address operands in memory must specify the segment value and the 16-bit offset value. for speed and compact instruction encoding, the seg- ment register used for physical address generation is implied by the addressing mode used (see table 5). figure 2. two-component address i/o space the i/o space consists of 64k 8-bit or 32k 16-bit ports. separate instructions (in, ins and out, outs) ad- dress the i/o space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the dx register. eight-bit port addresses are zero-ex- tended so that a15Ca8 are low. i/o port addresses 00f8h through 00ffh are reserved. the am186em and am188em microcontrollers provide specific in- structions for addressing i/o space. table 5. segment register selection rules 1 2 a 4 0 0 0 0 2 2 1 2 a 6 2 1 2 a 4 0 0 2 2 segment base logical address shift left 4 bits physical address to memory 15 0 19 0 19 0 15 0 15 0 offset memory reference needed segment register used implicit segment selection rule instructions code (cs) instructions (including immediate data) local data data (ds) all data references stack stack (ss) all stack pushes and pops; any memory references that use bp register external data (global) extra (es) all string instruction references that use the di register as an index
am186/188em and am186/188emlv microcontrollers 35 preliminary bus operation the industry-standard 80c186 and 80c188 microcon- trollers use a multiplexed address and data (ad) bus. the address is present on the ad bus only during the t 1 clock phase. the am186em and am188em microcon- trollers continue to provide the multiplexed ad bus and, in addition, provide a nonmultiplexed address (a) bus. the a bus provides an address to the system for the complete bus cycle (t 1 Ct 4 ). for systems where power consumption is a concern, it is possible to disable the address from being driven on the ad bus on the am186em microcontroller and on the ad and ao buses on the am188em microcontroller during the normal address portion of the bus cycle for accesses to ucs and/or lcs address spaces. in this mode, the affected bus is placed in a high impedance state during the address portion of the bus cycle. this feature is enabled through the da bits in the umcs and lmcs registers. when address disable is in effect, the number of signals that assert on the bus during all nor- mal bus cycles to the associated address space is re- duced, decreasing power consumption and reducing processor switching noise. on the am188em micro- controller, the address is driven on a015Ca08 during the data portion of the bus cycle, regardless of the set- ting of the da bits. if the aden pin is pulled low during processor reset, the value of the da bits in the umcs and lmcs registers is ignored and the address is driven on the ad bus for all ac- cesses, thus preserving the industry-standard 80c186 and 80c188 microcontrollers multiplexed address bus and providing support for existing emulation tools. the following diagrams show the am186em and am188em microcontroller bus cycles when the ad- dress bus disable feature is in effect. figure 3 shows the affected signals during a normal read or write operation for an am186em microcontrol- ler. the address and data will be multiplexed onto the ad bus. figure 4 shows an am186em microcontroller bus cycle when address bus disable is in effect. this results in having the ad bus operate in a nonmultiplexed ad- dress/data mode. the a bus will have the address dur- ing a read or write operation. figure 5 shows the affected signals during a normal read or write operation for an am188em microcontrol- ler. the multiplexed address/data mode is compatible with the 80c186 and 80c188 microcontrollers and might be used to take advantage of existing logic or pe- ripherals. figure 6 shows an am188em microcontroller bus cycle when address bus disable is in effect. the address and data is not multiplexed. the ad7Cad0 signals will have only data on the bus, while the ao bus will have the ad- dress during a read or write operation. figure 3. am186em microcontroller address busnormal read and write operation clkouta t 1 t 2 t 3 t 4 ad15Cad0 (read) data ad15Cad0 (write) lcs or ucs address data address address phase data phase a19Ca0 address mcs x, pcs x
36 am186/188em and am186/188emlv microcontrollers preliminary figure 4. am186em microcontrollerread and write with address bus disable in effect figure 5. am188em microcontroller address busnormal read and write operation clkouta t 1 t 2 t 3 t 4 ad15Cad0 (write) data lcs , ucs ad15Cad8 (read) ad7Cad0 (read) address phase data data phase data a19Ca0 address clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data ao15Cao8 (read or write) ad7Cad0 (write) address address data address address phase data phase a19Ca0 address lcs or ucs mcs x, pcs x
am186/188em and am186/188emlv microcontrollers 37 preliminary figure 6. am188em microcontrollerread and write with address bus disable in effect bus interface unit the bus interface unit controls all accesses to external peripherals and memory devices. external accesses include those to memory devices, as well as those to memory-mapped and i/o-mapped peripherals and the peripheral control block. the am186em and am188em microcontrollers provide an enhanced bus interface unit with the following features: n a nonmultiplexed address bus n separate byte write enables for high and low bytes in the am186em microcontroller only n pseudo static ram (psram) support the standard 80c186/188 multiplexed address and data bus requires system interface logic and an exter- nal address latch. on the am186em and am188em microcontrollers, new byte write enables, psram con- trol logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic. nonmultiplexed address bus the nonmultiplexed address bus (a19Ca0) is valid one-half clkouta cycle in advance of the address on the ad bus. when used in conjunction with the modi- fied ucs and lcs outputs and the byte write enable sig- nals, the a19Ca0 bus provides a seamless interface to sram, psram, and flash/eprom memory systems. byte write enables the am186em microcontroller provides the whb (write high byte) and wlb (write low byte) signals, which act as byte write enables. whb is the logical or of bhe and wr . whb is low when bhe and wr are both low. wlb is the logical or of ad0 and wr . wlb is low when ad0 and wr are both low. wb is low whenever a byte is written on the am188em microcontroller. the byte write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common srams. clkouta t 1 t 2 t 3 t 4 ad7Cad0 (read) data address ao15Cao8 lcs , ucs ad7Cad0 (write) data address phase data phase a19Ca0 address
38 am186/188em and am186/188emlv microcontrollers preliminary pseudo static ram (psram) support the am186em and am188em microcontrollers sup- port the use of psram devices in low memory chip-se- lect (lcs) space only. when psram mode is enabled, the timing for the lcs signal is modified by the chip-select control unit to provide a cs precharge period during psram accesses. the 40-mhz timing of the am186em and am188em microcontrollers is appropriate to allow 70-ns psram to run with one wait state. psram mode is enabled through a bit in the low memory chip-select (lmcs) register. the psram feature is disabled on cpu reset. in addition to the lcs timing changes for psram pre- charge, the psram devices also require periodic refresh of all internal row addresses to retain their data. although re- fresh of psram can be accomplished several ways, the am186em and am188em microcontrollers implement auto refresh only. the am186em and am188em microcontrollers gener- ate rfsh , a refresh signal, to the psram devices when psram mode is enabled. no refresh address is required by the psram when using the auto refresh mechanism. the rfsh signal is multiplexed with the mcs 3 signal pin. when psram mode is enabled, mcs 3 is not available for use as a chip-select signal. the refresh control unit must be programmed before accessing psram in lcs space. the refresh counter in the clock prescaler (cdram) register must be con- figured with the required refresh interval value. the ending address of lcs space and the ready and wait- state generation in the lmcs register must also be programmed. the refresh counter reload value in the cdram register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh. the refresh address counter must be set to 000000h to prevent another chip select from assert- ing. lcs is held high during a refresh cycle. the a bus is not used during refresh cycles. the lmcs register must be configured to external ready ignored (r2=1) with one wait state (r1Cr0=01b), and the psram mode enable bit (se) must be set. peripheral control block (pcb) the integrated peripherals of the am186em and am188em microcontrollers are controlled by 16-bit read/write registers. the peripheral registers are con- tained within an internal 256-byte control block. the registers are physically located in the peripheral de- vices they control, but they are addressed as a single 256-byte block. figure 7 shows a map of these regis- ters. reading and writing the pcb code that is intended to execute on the am188em mi- crocontroller should perform all writes to the pcb reg- isters as byte writes. these writes will transfer 16 bits of data to the pcb register even if an 8-bit register is named in the instruction. for example, out dx, al re- sults in the value of ax being written to the port address in dx . reads to the pcb should be done as word reads. code written in this manner will run correctly on the am188em microcontroller and on the am186em micro- controller. unaligned reads and writes to the pcb result in unpre- dictable behavior on both the am186em and am188em microcontrollers. for a complete description of all the registers in the pcb, see the am186em and am188em microcontrol- lers users manual , order# 19713.
am186/188em and am186/188emlv microcontrollers 39 preliminary figure 7. peripheral control block register map pcs and mcs auxiliary register a8 da memory partition register e0 pdcon register f0 reset configuration register f6 peripheral control block relocation register fe register name ww ww ww ww ww f4 offset (hexadecimal) e2 e4 d8 d6 d4 d2 ca c8 c6 c4 c2 c0 clock prescaler register enable rcu register dma 1 control register dma 1 transfer count register dma 1 destination address low register dma 1 source address high register dma 1 source address low register dma 0 control register dma 0 transfer count register dma 0 destination address high register dma 0 destination address low register d0 dma 0 source address low register dma 0 source address high register a6 a4 a2 a0 midrange memory chip select register peripheral chip select register low memory chip select register upper memory chip select register 80 serial port status register 82 84 serial port receive register 86 88 processor release level register dma 1 destination address high register serial port baud rate divisor register serial port transmit register serial port control register changed from 80c186 microcontroller. note : gaps in offset addresses indicate reserved registers.
40 am186/188em and am186/188emlv microcontrollers preliminary figure 7. peripheral control block register map (continued) offset (hexadecimal) int2 control register int1 control register int0 control register dma 1 interrupt control register dma 0 interrupt control register timer interrupt control register interrupt status register interrupt request register in-service register priority mask register interrupt mask register poll status register poll register end-of-interrupt register interrupt vector register 10 12 synchronous serial transmit 1 register 14 16 18 3e 40 42 pio mode 0 register 70 72 74 register name ww ww ww changed from 80c186 microcontroller. 44 76 78 7a note : gaps in offset addresses indicate reserved registers. 5c 5e 60 62 66 50 52 54 56 58 5a timer 2 mode/control register timer 2 maxcount compare a register timer 2 count register timer 1 mode/control register timer 1 maxcount compare b register timer 1 maxcount compare a register timer 1 count register timer 0 mode/control register timer 0 maxcount compare b register timer 0 maxcount compare a register timer 0 count register int3 control register 3c 3a 38 36 34 32 30 2e 2c 2a 28 26 24 22 20 pio data 1 register pio direction 1 register pio mode 1 register pio data 0 register pio direction 0 register serial port interrupt control register watchdog timer control register int4 control register synchronous serial receive register synchronous serial transmit 0 register synchronous serial enable register synchronous serial status register
am186/188em and am186/188emlv microcontrollers 41 preliminary clock and power management the clock and power management unit of the am186em and am188em microcontrollers includes a phase-locked loop (pll) and a second programmable system clock output (clkoutb). phase-locked loop (pll) in a traditional 80c186/188 design, the crystal frequency is twice that of the desired internal clock. because of the internal pll on the am186em and am188em microcontrollers, the internal clock generated by the am186em and am188em microcontrollers (clkouta) is the same frequency as the crystal. the pll takes the crystal inputs (x1 and x2) and generates a 45/55% (worst case) duty cycle intermediate system clock of the same frequency. this removes the need for an external 2x oscillator, reducing system cost. the pll is reset by an on-chip power-on reset (por) circuit. crystal-driven clock source the internal oscillator circuit of the am186em and am188em microcontrollers is designed to function with a parallel-resonant fundamental or third-overtone crys- tal. because of the pll, the crystal frequency should be equal to the processor frequency. do not replace a crystal with an lc or rc equivalent. the signals x1 and x2 are connected to an internal in- verting amplifier (oscillator) which provides, along with the external feedback loading, the necessary phase shift (figure 8). in such a positive feedback circuit, the inverting amplifier has an output signal (x2) 180 de- grees out of phase of the input signal (x1). the external feedback network provides an additional 180-degree phase shift. in an ideal system, the input to x1 will have 360 or zero degrees of phase shift. the ex- ternal feedback network is designed to be as close to ideal as possible. if the feedback network is not provid- ing necessary phase shift, negative feedback will dampen the output of the amplifier and negatively af- fect the operation of the clock generator. values for the loading on x1 and x2 must be chosen to provide the necessary phase shift and crystal operation. selecting a crystal when selecting a crystal, the load capacitance should always be specified (c l ). this value can cause variance in the oscillation frequency from the desired specified value (resonance). the load capacitance and the loading of the feedback network have the following relationship: where c s is the stray capacitance of the circuit. placing the crystal and c l in series across the inverting amplifier and tuning these values (c 1 , c 2 ) allows the crystal to os- cillate at resonance. this relationship is true for both fun- damental and third-overtone operation. finally, there is a relationship between c 1 and c 2 . to enhance the oscilla- tion of the inverting amplifier, these values need to be off- set with the larger load on the output (x2). equal values of these loads will tend to balance the poles of the inverting amplifier. the characteristics of the inverting amplifier set limits on the following parameters for crystals: esr (equivalent series resistance) ........... 80 ohm max drive level ..................................................................................... 1 mw max the recommended range of values for c 1 and c 2 are as follows: c 1 .............................................................................................................. 15 pf 20% c 2 .............................................................................................................. 22 pf 20% the specific values for c 1 and c 2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. figure 8. am186em and am188em microcontrollers oscillator configurations ( c 1 c 2 ) c l = (c 1 + c 2 ) + c s crystal am186em 200 pf note 1 note 1 : use for third overtone mode xtal frequency l1 value (max) 20 mhz 12 m h 20% 25 mhz 8.2 m h 20% 33 mhz 4.7 m h 20% 40 mhz 3.0 m h 20% x1 x2 b. crystal configuration a. inverting amplifier configuration c 1 c 2 crystal c 1 c 2 microcontroller
42 am186/188em and am186/188emlv microcontrollers preliminary external source clock alternately, the internal oscillator can be driven from an external clock source. this source should be con- nected to the input of the inverting amplifier (x1), with the output (x2) not connected. system clocks the base system clock of the 80c186 and 80c188 microcontrollers is renamed clkouta and the additional output is called clkoutb. clkouta and clkoutb operate at either the processor frequency or the crystal input frequency. the output drivers for both clocks are individually programmable for disable. figure 9 shows the organization of the clocks. the second clock output (clkoutb) allows one clock to run at the crystal input frequency and the other clock to run at the power-save frequency. individual drive en- able bits allow selective enabling of just one or both of these clock outputs. figure 9. clock organization power-save operation the power-save mode of the am186em and am188em microcontrollers reduces power consump- tion and heat dissipation, thereby extending battery life in portable systems. in power-save mode, operation of the cpu and internal peripherals continues at a slower clock frequency. when an interrupt occurs, the micro- controller automatically returns to its normal operating frequency on the internal clocks next rising edge of t 3 . in order for an interrupt to be recognized, it must be valid before the internal clocks rising edge of t 3 . note: power-save operation requires that clock-de- pendent devices be reprogrammed for clock frequency changes. software drivers must be aware of clock fre- quency. initialization and processor reset processor initialization or startup is accomplished by driving the res input pin low. res must be held low for 1 ms during power-up to ensure proper device initializa- tion. res forces the am186em and am188em microcon- trollers to terminate all execution and local bus activity. no instruction or bus activity occurs as long as res is active. after res becomes inactive and an internal processing in- terval elapses, the microcontroller begins execution with the instruction at physical location ffff0h. res also sets some registers to predefined values. the reset configuration register when the res input is asserted low, the contents of the address/data bus (ad15Cad0) are written into the reset configuration register. the system can place configura- tion information on the address/data bus using weak ex- ternal pullup or pulldown resistors, or using an external driver that is enabled during reset. the processor does not drive the address/data bus during reset. for example, the reset configuration register could be used to provide the software with the position of a con- figuration switch in the system. using weak external pullup and pulldown resistors on the address and data bus, the system would provide the microcontroller with a value corresponding to the position of the jumper dur- ing a reset. pll power-save divisor (/2 to /128) mux clkouta clkoutb drive enable drive enable x1, x2 processor internal clock time delay 6 2.5ns mux
am186/188em and am186/188emlv microcontrollers 43 preliminary chip-select unit the am186em and am188em microcontrollers con- tain logic that provides programmable chip-select gen- eration for both memories and peripherals. the logic can be programmed to provide ready and wait-state generation and latched address bits a1 and a2. the chip-select lines are active for all memory and i/o cy- cles in their programmed areas, whether they are gen- erated by the cpu or by the integrated dma unit. the am186em and am188em microcontrollers pro- vide six chip-select outputs for use with memory de- vices and six more for use with peripherals in either memory space or i/o space. the six chip selects for memory devices can be used to address three memory ranges. each of the six peripheral chip selects ad- dresses a 256-byte block that is offset from a program- mable base address. a read or write access to the corresponding chip select register activates the chip selects. chip-select timing the timing for the ucs and lcs outputs is modified from the original 80c186 microcontroller. these outputs now assert in conjunction with the nonmultiplexed address bus for normal memory timing. to allow these outputs to be available earlier in the bus cycle, the number of program- mable memory size selections has been reduced. ready and wait-state programming the am186em and am188em microcontrollers can be programmed to sense a ready signal for each of the pe- ripheral or memory chip-select lines. the ready signal can be either the ardy or srdy signal. each chip-se- lect control register (umcs, lmcs, mmcs, pacs, and mpcs) contains a single-bit field that determines whether the external ready signal is required or ig- nored. the number of wait states to be inserted for each ac- cess to a peripheral or memory region is programma- ble. the chip-select control registers for ucs , lcs , mcs 3 Cmcs 0, pcs 6, and pcs 5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. pcs 3Cpcs 0 use three bits to pro- vide additional values of 5, 7, 9, and 15 wait states. when external ready is required, internally pro- grammed wait states will always complete before ex- ternal ready can terminate or extend a bus cycle. for example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. if external ready is as- serted at that time, the access completes after six cy- cles (four cycles plus two wait states). if external ready is not asserted during the first wait state, the access is extended until ready is asserted, which is followed by one more wait state followed by t 4 . chip-select overlap although programming the various chip selects on the am186em and am188em microcontrollers so that mul- tiple chip select signals are asserted for the same physical address is not recommended, it may be un- avoidable in some systems. in such systems, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. the peripheral control block (pcb) is accessed using internal signals. these internal signals function as chip selects configured with zero wait states and no external ready. therefore, the pcb can be programmed to ad- dresses that overlap external chip select signals if those external chip selects are programmed to zero wait states with no external ready required. when overlapping an additional chip select with either the lcs or ucs chip selects, it must be noted that set- ting the disable address (da) bit in the lmcs or umcs register will disable the address from being driven on the ad bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. the mcs and pcs chip select pins can be configured as either chip selects (normal function) or as pio inputs or outputs. it should be noted; however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip se- lects or pios. this means that if these chip selects are enabled (by a read or write to the mmcs and mpcs for the mcs chip selects, or by a read or write to the pacs and mpcs registers for the pcs chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip se- lects with which their assertion would overlap if they were configured as chip selects. although the pcs 4 signal is not available on an exter- nal pin, the ready and wait state logic for this signal still exists internal to the part. for this reason, the pcs 4 ad- dress space must follow the rules for overlapping chip selects. the ready and wait-state logic for pcs 6C pcs 5 is disabled when these signals are configured as address bits a2Ca1. failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting for a ready signal. this behavior may occur even in a system in which ready is always asserted (ardy or srdy tied high).
44 am186/188em and am186/188emlv microcontrollers preliminary configuring pcs in i/o space with lcs or any other chip select configured for memory address 0 is not con- sidered overlapping of the chip selects. overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address. upper memory chip select the am186em and am188em microcontrollers pro- vide a ucs chip select for the top of memory. on reset, the am186em and am188em microcontrollers begin fetching and executing instructions starting at memory lo- cation ffff0h. therefore, upper memory is usually used as instruction memory. to facilitate this usage, ucs de- faults to active on reset, with a default memory range of 64 kbytes from f0000h to fffffh, with external ready re- quired and three wait states automatically inserted. the ucs memory range always ends at fffffh. the lower boundary is programmable. low memory chip select the am186em and am188em microcontrollers pro- vide an lcs chip select for the bottom of memory. since the interrupt vector table is located at the bottom of mem- ory starting at 00000h, the lcs pin is usually used to con- trol data memory. the lcs pin is not active on reset. midrange memory chip selects the am186em and am188em microcontrollers pro- vide four chip selects, mcs 3 Cmcs 0, for use in a user- locatable memory block. the base address of the memory block can be located anywhere within the 1-mbyte mem- ory address space, exclusive of the areas associated with the ucs and lcs chip selects, as well as the address range of the peripheral chip selects, pcs 6, pcs 5, and pcs 3Cpcs 0, if they are mapped to memory. the mcs address range can overlap the pcs address range if the pcs chip selects are mapped to i/o space. unlike the ucs and lcs chip selects, the mcs outputs assert with the multiplexed ad address bus. peripheral chip selects the am186em and am188em microcontrollers pro- vide six chip selects, pcs 6Cpcs 5 and pcs 3Cpcs 0, for use within a user-locatable memory or i/o block. pcs 4 is not available on the am186em and am188em microcontrollers. the base address of the memory block can be located anywhere within the 1-mbyte memory address space, exclusive of the areas associ- ated with the ucs , lcs , and mcs chip selects, or they can be configured to access the 64 kbyte i/o space. the pcs pins are not active on reset. pcs 6Cpcs 5 can have from zero to three wait states. pcs 3Cpcs 0 can have four additional wait-state values5, 7, 9, and 15. unlike the ucs and lcs chip selects, the pcs outputs assert with the multiplexed ad address bus. note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by periph- eral chip selects in the 80c186 and 80c188 microcontrol- lers.
am186/188em and am186/188emlv microcontrollers 45 preliminary refresh control unit the refresh control unit (rcu) automatically gener- ates refresh bus cycles. after a programmable period of time, the rcu generates a memory read request to the bus interface unit. the rcu is fixed to three wait states for the psram auto refresh mode. if the hlda pin is active when a refresh request is gen- erated (indicating a bus hold condition), then the am186em and am188em microcontrollers deactivate the hlda pin in order to perform a refresh cycle. the external bus master must remove the hold signal for at least one clock in order to allow the refresh cycle to execute. the sequence of hlda going inactive while hold is being held active can be used to signal a pending refresh request. interrupt control unit the am186em and am188em microcontrollers can re- ceive interrupt requests from a variety of sources, both internal and external. the internal interrupt controller arranges these requests by priority and presents them one at a time to the cpu. there are six external interrupt sources on the am186em and am188em microcontrollersfive maskable interrupt pins and one nonmaskable interrupt pin. in addition, there are six total internal interrupt sourcesthree timers, two dma channels, and the asynchronous serial portthat are not connected to external pins. the am186em and am188em microcontrollers pro- vide three interrupt sources not present on the am186 and am188 microcontrollers. the first is an additional external interrupt pin (int4). this pin operates much like the already existing interrupt pins (int3Cint0). the second is an internal watchdog timer interrupt. the third is an internal interrupt from the asynchronous se- rial port. the five maskable interrupt request pins can be used as direct interrupt requests, or they can be cascaded with an 82c59a-compatible external interrupt control- ler if more inputs are needed. an external interrupt con- troller can be used as the system master by programming the internal interrupt controller to operate in slave mode. in all cases, nesting can be enabled so that interrupt service routines for lower priority inter- rupts are interrupted by a higher priority interrupt.
46 am186/188em and am186/188emlv microcontrollers preliminary timer control unit there are three 16-bit programmable timers in the am186em and am188em microcontrollers. timer 0 and timer 1 are connected to four external pins (each one has an input and an output). these two timers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle waveforms. in ad- dition, timer 1 can be configured as a watchdog timer interrupt. the watchdog timer interrupt provides a mechanism for detecting software crashes or hangs. the tmrout1 output is internally connected to the watchdog timer in- terrupt. the timer1 count register must then be re- loaded at intervals less than the timer1 max count to assure the watchdog interrupt is not taken. if the code crashes or hangs, the timer1 countdown will cause a watchdog interrupt. timer 2 is not connected to any external pins. it can be used for real-time coding and time-delay applications. it can also be used as a prescale to timers 0 and 1 or as a dma request source. the timers are controlled by eleven 16-bit registers in the peripheral control block. a timers timer-count reg- ister contains the current value of that timer. the timer- count register can be read or written with a value at any time, regardless of whether the timer is running. the microcontroller increments the value of the timer-count register each time a timer event occurs. each timer also has a maximum-count register that de- fines the maximum value the timer will reach. when the timer reaches the maximum value, it resets to 0 during the same clock cyclethe value in the maximum-count register is never stored in the timer-count register. also, timers 0 and 1 have a secondary maximum-count register. using both the primary and secondary maxi- mum-count registers lets the timer alternate between two maximum values. if the timer is programmed to use only the primary max- imum-count register, the timer output pin switches low for one clock cycle after the maximum value is reached. if the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. the duty cycle of the waveform depends on the values in the maximum- count registers. each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter the internal clock frequency. a timer can be clocked exter- nally at this same frequency; however, because of in- ternal synchronization and pipelining of the timer circuitry, the timer output may take up to six clock cy- cles to respond to the clock or gate input. direct memory access (dma) direct memory access (dma) permits transfer of data between memory and peripherals without cpu involve- ment. the dma unit in the am186em and am188em microcontrollers, shown in figure 10, provides two high-speed dma channels. data transfers can occur be- tween memory and i/o spaces (e.g., memory to i/o) or within the same space (e.g., memory-to-memory or i/o-to- i/o). in addition, either bytes or words can be transferred to or from even or odd addresses on the am186em micro- controller. the am188em microcontroller does not sup- port word transfers. only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. each channel accepts a dma request from one of three sourcesthe channel request pin (drq1C drq0), timer 2, or the system software. the channels can be programmed with different priorities in the event of a simultaneous dma request or if there is a need to interrupt transfers on the other channel. dma operation each channel has six registers in the peripheral control block that define specific channel operations. the dma registers consist of a 20-bit source address (2 regis- ters), a 20-bit destination address (2 registers), a 16-bit transfer count register, and a 16-bit control register. the dma transfer count register (dtc) specifies the number of dma transfers to be performed. up to 64k byte or word transfers can be performed with automatic termination. the dma control registers define the channel operation. all registers can be modified dur- ing any dma activity. any changes made to the dma registers are reflected immediately in dma operation. table 6. am186em microcontroller maximum dma transfer rates type of synchronization selected maximum dma transfer rate (mbyte/s) 40 mhz 33 mhz 25 mhz 20 mhz unsynchronized 10 8.25 6.25 5 source synch 10 8.25 6.25 5 destination synch (cpu needs bus) 6.6 5.5 4.16 3.3 destination synch (cpu does not need bus) 8 6.6 5 4
am186/188em and am186/188emlv microcontrollers 47 preliminary figure 10. dma unit block diagram dma channel control registers each dma control register determines the mode of op- eration for the particular dma channel. this register specifies the following: n the mode of synchronization n whether bytes or words are transferred n if an interrupt is generated after the last transfer n if dma activity ceases after a programmed number of dma cycles n the relative priority of the dma channel with re- spect to the other dma channel n whether the source address is incremented, decre- mented, or maintained constant after each transfer n whether the source address addresses memory or i/o space n whether the destination address is incremented, decremented, or maintained constant after trans- fers n whether the destination address addresses mem- ory or i/o space dma priority the dma channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have dma requests pending. dma cycles always have priority over internal cpu cycles, except between locked memory accesses or word accesses to odd memory locations. however, an external bus hold takes priority over an internal dma cycle. because an interrupt request cannot suspend a dma operation and the cpu cannot access memory during a dma cycle, interrupt latency time suffers during se- quences of continuous dma cycles. an nmi request, however, causes all internal dma activity to halt. this allows the cpu to respond quickly to the nmi request. source address ch. 1 source address ch. 0 20-bit adder/subtractor dma control logic request selection logic adder control logic 20 20 channel control register 1 channel control register 0 16 drq1 drq0 internal address/data bus timer request interrupt request transfer counter ch. 1 destination address ch. 1 destination address ch. 0 transfer counter ch. 0
48 am186/188em and am186/188emlv microcontrollers preliminary asynchronous serial port the am186em and am188em microcontrollers pro- vide an asynchronous serial port. the asynchronous serial port is a two-pin interface that permits full-duplex bidirectional data transfer. the asynchronous serial port supports the following features: n full-duplex operation n 7-bit or 8-bit data transfers n odd, even, or no parity n 1 or 2 stop bits if additional rs-232 signals are required, they can be created with available pio pins. the asynchronous se- rial port transmit and receive sections are double buff- ered. break character, framing, parity, and overrun error detection are provided. exception interrupt gener- ation is programmable by the user. the transmit/receive clock is based on the internal pro- cessor clock, which is divided down internally to the se- rial port operating frequency. the serial port permits 7- bit and 8-bit data transfers. dma transfers through the serial port are not supported. the serial port generates one interrupt for any of three serial port eventstransmit complete, data received, and error. the serial port can be used in power-save mode, but the software must adjust the transfer rate to correctly reflect the new internal operating frequency and must ensure that the serial port does not receive any infor- mation while the frequency is being changed. synchronous serial interface the synchronous serial interface (ssi) lets the am186em and am188em microcontrollers communi- cate with application-specific integrated circuits (asics) that require reprogrammability but are short on pins. this four-pin interface permits half-duplex, bidi- rectional data transfer at speeds of up to 20 mbits/sec. unlike the asynchronous serial port, the ssi operates in a master/slave configuration. the am186em and am188em microcontrollers are the master port. the ssi interface provides four pins for communicating with system components: two enables (sden0 and sden1), a clock (sclk), and a data pin (sdata). five registers are used to control and monitor the interface. four-pin interface the two enable pins sden1Csden0 can be used di- rectly as enables for up to two peripheral devices. transmit and receive operations are synchronized be- tween the master (am186em and am188em micro- controllers) and slave (peripheral) by means of the sclk output. sclk is derived from the internal proces- sor clock and is the processor clock divided by 2, 4, 8, or 16.
am186/188em and am186/188emlv microcontrollers 49 preliminary figure 11. synchronous serial interface multiple write figure 12. synchronous serial interface multiple read sclk sden sdata write to ssc, bit de=1 write to ssd poll sss for pb=0 write to ssd poll sss for pb=0 write to ssd write to ssc, bit de=0 poll sss for pb=0 pb=0 dr/dt=0 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=0 dr/dt=0 sclk sden sdata write to ssc, bit de=1 write to ssd poll sss for pb=0 read from ssr (dummy) poll sss for pb=0 read from ssr write to ssc, bit de=0 poll sss for pb=0 pb=0 dr/dt=0 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=1 dr/dt=0 pb=0 dr/dt=1 pb=0 dr/dt=0 read from ssr
50 am186/188em and am186/188emlv microcontrollers preliminary programmable i/o (pio) pins there are 32 pins on the am186em and am188em mi- crocontrollers that are available as user multipurpose signals. table 2 and table 3 on page 30 list the pio pins. each of these pins can be used as a user-pro- grammable input or output signal if the normal shared function is not needed. if a pin is enabled to function as a pio signal, the pre- assigned signal function is disabled and does not affect the level on the pin. a pio signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. after power-on reset, the pio pins default to various configurations. the column titled power-on reset sta- tus in table 2 and table 3 on page 30 lists the defaults for the pios. the system initialization code must reconfigure the pios as required. the a19Ca17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address ffff0h. the dt/r , den , and srdy pins also default to normal operation on power-on reset. note that emulators use a19, a18, a17, s6, and uzi . if the ad15Cad0 bus override is enabled on power-on reset, then s6 / clkdiv 2 and uzi revert to normal opera- tion instead of pio input with pullup. if bhe /aden (186) or rfsh 2/aden (188) is held low during power-on reset the ad15Cad0 bus override is enabled.
am186/188em and am186/188emlv microcontrollers 51 preliminary absolute maximum ratings storage temperature am186em/am188em ..................... C65 c to +125 c am186emlv/am188emlv............. C65 c to +125 c voltage on any pin with respect to ground am186/188em ........................... C0.5 v to v cc +0.5 v am186/188emlv ....................... C0.5 v to v cc +0.5 v note: stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. ex- posure to absolute maximum ratings for extended peri- ods may affect device reliability. operating ranges operating ranges define those limits between which the functionality of the device is guaranteed. am186em/am188em microcontrollers commercial (t c ) .................................0 c to +100 c industrial* (t a )...................................C40 c to +85 c v cc up to 33 mhz ..................................... 5 v 10% v cc greater than 33 mhz............................ 5 v 5% am186emlv/am188emlv microcontrollers commercial (t a ) ................................... 0 c to +70 c v cc up to 25 mhz ................................. 3.3 v 0.3 v where: t c = case temperature t a = ambient temperature *industrial versions of am186em and am188em microcontrol- lers are available in 20 and 25 mhz operating frequencies only. dc characteristics over commercial operating range notes: a the lcs /once 0 , mcs 3Cmcs 0 , ucs /once 1 , and rd pins have weak internal pullup resistors. loading the lcs /once 0 and ucs /once 1 pins in excess of i oh = C200 m a during reset can cause the device to go into once mode. b current is measured with the device in reset with x1 and x2 driven, and all other non-power pins open but held high or low. c power supply current for the am186emlv and am188emlv microcontrollers, which are available in 20 and 25 mhz operating frequencies only. d testing is performed with the pins floating, either during hold or by invoking the once mode. preliminary symbol parameter description test conditions min max unit v il input low voltage (except x1) C0.5 0.8 v v il1 clock input low voltage (x1) C0.5 0.8 v v ih input high voltage (except res and x1) 2.0 v cc + 0.5 v v ih1 input high voltage (res ) 2.4 v cc + 0.5 v v ih2 clock input high voltage (x1) v cc C 0.8 v cc + 0.5 v v ol output low voltage am186em and am188em i ol = 2.5 ma (s 2Cs 0) i ol = 2.0 ma (others) 0.45 v am186emlv and am188emlv i ol = 1.5 ma (s 2Cs 0) i ol = 1.0 ma (others) 0.45 v v oh output high voltage (a) am186em and am188em i oh = C2.4 ma @ 2.4 v 2.4 v cc +0.5 v i oh = C200 m a @ v cc C0.5 v cc C0.5 v cc v am186emlv and am188emlv i oh = C200 m a @ v cc C0.5 v cc C0.5 v cc v i cc power supply current @ 0 c am186em and am188em v cc = 5.5 v (b) 5.9 ma/ mhz am186emlv and am188emlv v cc = 3.6 v (b) 2.75 ma/ mhz v ol output low voltage i ol = 2.5 ma (s 2Cs 0) i ol = 2.0 ma (others) 0.45 v i li input leakage current @ 0.5 mhz 0.45 v v in v cc 10 m a i lo output leakage current @ 0.5 mhz 0.45 v v out v cc (d) 10 m a v clo clock output low i clo = 4.0 ma 0.45 v v cho clock output high i cho = C500 m a v cc C 0.5 v
52 am186/188em and am186/188emlv microcontrollers preliminary dc characteristics over commercial operating range (continued) a measured with a device running. not tested and not guaranteed. b power supply current for the am186emlv and am188emlv microcontrollers, which are available in 20 and 25 mhz operating frequencies only. c power is measured while device is operating. not tested and not guaranteed. capacitance note: capacitance limits are guaranteed by characterization. preliminary symbol parameter description test conditions typical unit nominal i cc typical power supply current @ 25 c v cc = 5.5 v (a) 4.5 ma/ mhz nominal i cc am186emlv and am188emlv typical power supply current @ 25 c v cc = 3.6 v (a) (b) 3.0 ma/ mhz peak i cc measured peak i cc v cc = 5.5 v (c) 5.9 ma/ mhz peak i cc am186emlv and am188emlv measured peak i cc v cc = 3.6 v (b) (c) 4.0 ma/ mhz preliminary symbol parameter description test conditions min max unit c in input capacitance @ 1 mhz 10 pf c io output or i/o capacitance @ 1 mhz 20 pf
am186/188em and am186/188emlv microcontrollers 53 preliminary power supply current for the typical system specification shown in figure 13, i cc has been measured at 3.0 ma per mhz of system clock. for the typical system specification shown in fig- ure 14, i cc has been measured at 4.5 ma per mhz of sys- tem clock. the typical system is measured while the system is executing code in a typical application with max- imum voltage and at room temperature. actual power sup- ply current is dependent on system design and may be greater or less than the typical i cc figure presented here. typical current in figure 13 is given by: ................. i cc = 3.0 ma freq(mhz). typical current in figure 14 is given by: ................. i cc = 4.5 ma freq(mhz). please note that dynamic i cc measurements are de- pendent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the out- puts. for these i cc measurements, the devices were set to the following modes: n no dc loads on the output buffers n output capacitive load set to 35 pf n ad bus set to data only n pios are disabled n timer, serial port, refresh, and dma are enabled table 7 shows the variables that are used to calculate the typical power consumption value for each version of the am186emlv and am188emlv microcontrol- lers. table 7. typical power consumption calculation for the am186emlv and am188emlv figure 13. typical i cc versus frequency for the am186emlv and am188emlv figure 14. typical i cc versus frequency for the am186em and am188em mhz i cc volts / 1000 = p typical power in watts mhz typical i cc volts 16 3.0 3.6 0.173 20 3.0 3.6 0.216 25 3.0 3.6 0.270 clock frequency (mhz) i cc (ma) 25 mhz 20 mhz 0 20 40 60 80 100 120 140 10 20 30 16 mhz clock frequency (mhz) i cc (ma) 0 40 80 120 160 200 240 280 10 20 30 40 20 mhz 25 mhz 33 mhz 40 mhz
54 am186/188em and am186/188emlv microcontrollers preliminary thermal characteristics tqfp package the am186em and am188em microcontrollers are specified for operation with case temperature ranges from 0 c to +100 c for a commercial temperature de- vice. case temperature is measured at the top center of the package as shown in figure 15. the various tem- peratures and thermal resistances can be determined using the equations in figure 16 with information given in table 8. q ja is the sum of q jc and q ca . q jc is the internal ther- mal resistance of the assembly. q ca is the case to am- bient thermal resistance. the variable p is power in watts. typical power supply current (i cc ) for the am186em and am188em microcontrollers is 5.9 ma per mhz of clock frequency. figure 15. thermal resistance( c/watt) figure 16. thermal characteristics equations table 8. thermal characteristics ( c/watt) q ja q ca q jc q ja = q jc + q ca t c package/board airflow (linear feet per minute) q jc q ca q ja pqfp/2-layer 0 fpm 7 38 45 200 fpm 7 32 39 400 fpm 7 28 35 600 fpm 7 26 33 tqfp/2-layer 0 fpm 10 46 56 200 fpm 10 36 46 400 fpm 10 30 40 600 fpm 10 28 38 pqfp/4-layer to 6-layer 0 fpm 5 18 23 200 fpm 5 16 21 400 fpm 5 14 19 600 fpm 5 12 17 tqfp/4-layer to 6-layer 0 fpm 6 24 30 200 fpm 6 22 28 400 fpm 6 20 26 600 fpm 6 18 24 q ja = q jc + q ca p=5.9 ma freq (mhz) v cc t j =t c +( p q jc ) t j =t a + (p q ja ) t c =t j C( p q jc ) t c =t a +( p q ca ) t a =t j C( p q ja ) t a =t c C( p q ca )
am186/188em and am186/188emlv microcontrollers 55 preliminary typical ambient temperatures the typical ambient temperature specifications are based on the following assumptions and calculations: the commercial operating range of the am186em and am188em microcontrollers is a case temperature t c of 0 to 100 degrees centigrade. t c is measured at the top center of the package. an increase in the ambient tem- perature causes a proportional increase in t c . the 40-mhz microcontroller is specified as 5.0 v, plus or minus 5%. therefore, 5.25 v is used for calculating typical power consumption on the 40-mhz microcon- troller. microcontrollers up to 33 mhz are specified as 5.0 v, plus or minus 10%. therefore, 5.5 v is used for calcu- lating typical power consumption up to 33 mhz. typical power supply current (i cc ) in normal usage is es- timated at 5.9 ma per mhz of microcontroller clock rate. typical power consumption (watts) = (5.9 ma/mhz) times microcontroller clock rate times voltage divided by 1000. table 9 shows the variables that are used to calculate the typical power consumption value for each version of the am186em and am188em microcontrollers. table 9. typical power consumption calculation thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. a safe operating range for the device can be calculated using the following formulas from figure 16 and the variables in table 8. by using the maximum case rating t c , the typical power consumption value from table 9, and q jc from table 8, the junction temperature t j can be calculated by using the following formula from figure 16. t j = t c + ( p q jc ) table 10 shows t j values for the various versions of the am186em and am188em microcontrollers. the column titled speed/pkg/board in table 10 indicates the clock speed in mhz, the type of package (p for pqfp and t for tqfp), and the type of board (2 for 2-layer and 4C6 for 4- layer to 6-layer). table 10. junction temperature calculation by using t j from table 10, the typical power consumption value from table 9, and a q ja value from table 8, the typ- ical ambient temperature t a can be calculated using the following formula from figure 16. t a = t j C ( p q ja ) for example, t a for a 40-mhz pqfp design with a 2- layer board and 0 fpm airflow is calculated as follows: t a = 108.673 C ( 1.239 45 ) t a = 52.918 in this calculation, t j comes from table 10, p comes from table 9, and q ja comes from table 8. see table 11. t a for a 33-mhz tqfp design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: t a = 106.4251 C ( 1.07085 28 ) t a = 76.4413 see table 14 for the result of this calculation. table 11 through table 14 and figure 17 through fig- ure 20 show t a based on the preceding assumptions and calculations for a range of q ja values with airflow from 0 linear feet per minute to 600 linear feet per minute. p = mhz i cc volts / 1000 typical power (p) in watts mhz typical i cc volts 40 5.9 5.25 1.239 33 5.9 5.5 1.07085 25 5.9 5.5 0.81125 20 5.9 5.5 0.649 speed/ pkg/ board t j = t c + ( p q jc ) t j t c p q jc 40/p2 100 1.239 7 108.7 40/t2 100 1.239 10 112.4 40/p4C6 100 1.239 5 106.2 40/t4C6 100 1.239 6 107.4 33/p2 100 1.07085 7 107.5 33/t2 100 1.07085 10 110.7 33/p4C6 100 1.07085 5 105.3 33/t4C6 100 1.07085 6 106.4 25/p2 100 0.81125 7 105.7 25/t2 100 0.81125 10 108.1 25/p4C6 100 0.81125 5 104.1 25/t4C6 100 0.81125 6 104.9 20/p2 100 0.649 7 104.5 20/t2 100 0.649 10 106.5 20/p4C6 100 0.649 5 103.2 20/t4C6 100 0.649 6 103.9
56 am186/188em and am186/188emlv microcontrollers preliminary table 11 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used with a 2-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case tempera- ture. figure 17 illustrates the typical temperatures in table 11. table 11. typical ambient temperatures for pqfp with 2-layer board figure 17. typical ambient temperatures for pqfp with 2-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 52.918 60.352 65.308 67.786 33 mhz 1.07085 59.3077 65.7328 70.0162 72.1579 25 mhz 0.81125 69.1725 74.04 77.285 78.9075 20 mhz 0.649 75.338 79.232 81.828 83.126 airflow (linear feet per minute) 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 40 50 60 70 80 90 l l l l v v v v u u u u n n n n
am186/188em and am186/188emlv microcontrollers 57 preliminary table 12 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used with a 2-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case tempera- ture. figure 18 illustrates the typical temperatures in table 12. table 12. typical ambient temperatures for tqfp with 2-layer board figure 18. typical ambient temperatures for tqfp with 2-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 43.006 55.396 62.83 65.308 33 mhz 1.07085 50.7409 61.4494 67.8745 70.0162 25 mhz 0.81125 62.6825 70.795 75.6625 77.285 20 mhz 0.649 70.146 76.636 80.53 81.828 airflow (linear feet per minute) l l l l v v v v u u u u n n n n 0 fpm 200 fpm 400 fpm 600 fpm l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 40 50 60 70 80 90 typical ambient temperature (degrees c)
58 am186/188em and am186/188emlv microcontrollers preliminary table 13 shows typical maximum ambient temperatures in degrees centigrade for a pqfp package used with a 4-layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 19 illustrates the typical temperatures in table 13. table 13. typical ambient temperatures for pqfp with 4-layer to 6-layer board figure 19. typical ambient temperatures for pqfp with 4-layer to 6-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 77.698 80.176 82.654 85.132 33 mhz 1.07085 80.7247 82.8664 85.0081 87.1498 25 mhz 0.81125 85.3975 87.02 88.6425 90.265 20 mhz 0.649 88.318 89.616 90.914 92.212 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: 70 75 80 85 90 95 airflow (linear feet per minute) l l l l v v v v u u u u n n n n
am186/188em and am186/188emlv microcontrollers 59 preliminary table 14 shows typical maximum ambient temperatures in degrees centigrade for a tqfp package used with a 4-layer to 6-layer board. the typical ambient temperatures are based on a 100-degree centigrade maximum case temperature. figure 20 illustrates the typical temperatures in table 14. table 14. typical ambient temperatures for tqfp with 4-layer to 6-layer board figure 20. typical ambient temperatures for tqfp with 4-layer to 6-layer board microcontroller speed typical power (watts) linear feet per minute airflow 0 fpm 200 fpm 400 fpm 600 fpm 40 mhz 1.239 70.264 72.742 75.22 77.698 33 mhz 1.07085 74.2996 76.4413 78.583 80.7247 25 mhz 0.81125 80.53 82.1525 83.775 85.3975 20 mhz 0.649 84.424 85.722 87.02 88.318 0 fpm 200 fpm 400 fpm 600 fpm typical ambient temperature (degrees c) 70 75 80 85 90 95 l 40 mhz n 20 mhz u 25 mhz u 33 mhz legend: airflow (linear feet per minute) l l l l v v v v u u u u n n n n
60 am186/188em and am186/188emlv microcontrollers preliminary commercial switching characteristics and waveforms in the switching waveforms that follow, several abbre- viations are used to indicate the specific periods of a bus cycle. these periods are referred to as time states. a typical bus cycle is composed of four consecutive time states: t 1 , t 2 , t 3 , and t 4 . wait states, which represent multiple t 3 states, are referred to as t w states. when no bus cycle is pending, an idle (t i ) state occurs. in the switching parameter descriptions, the multi- plexed address is referred to as the ad address bus; the demultiplexed address is referred to as the a address bus. key to switching waveforms must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform input output invalid invalid
am186/188em and am186/188emlv microcontrollers 61 preliminary alphabetical key to switching parameter symbols note: the following parameters are not defined or used as this time: 41, 56, 60, 73, 74, 76. parameter symbol no. description parameter symbol no. description t arych 49 ardy resolution transition setup time t cldx 2 data in hold t arychl 51 ardy inactive holding time t clev 71 clkouta low to sden valid t arylcl 52 ardy setup time t clhav 62 hlda valid delay t avbl 87 a address valid to whb , wlb low t clrf 82 clkouta high to rfsh invalid t avch 14 ad address valid to clock high t clrh 27 rd inactive delay t avll 12 ad address valid to ale low t clrl 25 rd active delay t avrl 66 a address valid to rd low t clsh 4 status inactive delay t avwl 65 a address valid to wr low t clsl 72 clkouta low to sclk low t azrl 24 ad address float to rd active t clsry 48 srdy transition hold time t ch1ch2 45 clkouta rise time t cltmv 55 timer output delay t chav 68 clkouta high to a address valid t coaob 83 clkouta to clkoutb skew t chck 38 x1 high time t cvctv 20 control active delay 1 t chcl 44 clkouta high time t cvctx 31 control inactive delay t chcsv 67 clkouta high to lcs /ucs valid t cvdex 21 den inactive delay t chcsx 18 mcs /pcs inactive delay t cxcsx 17 mcs /pcs hold from command inactive t chctv 22 control active delay 2 t dvcl 1 data in setup t chcv 64 command lines valid delay (after float) t dvsh 75 data valid to sclk high t chcz 63 command lines float delay t dxdl 19 den inactive to dt/r low t chdx 8 status hold time t hvcl 58 hold setup t chlh 9 ale active delay t invch 53 peripheral setup time t chll 11 ale inactive delay t invcl 54 drq setup time t chrfd 79 clkouta high to rfsh valid t lcrf 86 lcs inactive to rfsh active delay t chsv 3 status active delay t lhav 23 ale high to address valid t cicoa 69 x1 to clkouta skew t lhll 10 ale width t cicob 70 x1 to clkoutb skew t llax 13 ad address hold from ale inactive t ckhl 39 x1 fall time t lock 61 maximum pll lock time t ckin 36 x1 period t lrll 84 lcs precharge pulse width t cklh 40 x1 rise time t resin 57 res setup time t cl2cl1 46 clkouta fall time t rfcy 85 rfsh cycle time t clarx 50 ardy active hold time t rhav 29 rd inactive to ad address active t clav 5 ad address valid delay t rhdx 59 rd high to data hold on ad bus t clax 6 address hold t rhlh 28 rd inactive to ale high t claz 15 ad address float delay t rlrh 26 rd pulse width t clch 43 clkouta low time t shdx 77 sclk high to spi data hold t clck 37 x1 low time t sldv 78 sclk low to spi data valid t clcl 42 clkouta period t srycl 47 srdy transition setup time t clclx 80 lcs inactive delay t whdex 35 wr inactive to den inactive t clcsl 81 lcs active delay t whdx 34 data hold after wr t clcsv 16 mcs /pcs active delay t whlh 33 wr inactive to ale high t cldox 30 data hold time t wlwh 32 wr pulse width t cldv 7 data valid delay
62 am186/188em and am186/188emlv microcontrollers preliminary numerical key to switching parameter symbols note: the following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76. number parameter symbol description number parameter symbol description 1 t dvcl data in setup 43 t clch clkouta low time 2 t cldx data in hold 44 t chcl clkouta high time 3 t chsv status active delay 45 t ch1ch2 clkouta rise time 4 t clsh status inactive delay 46 t cl2cl1 clkouta fall time 5 t clav ad address valid delay 47 t srycl srdy transition setup time 6 t clax address hold 48 t clsry srdy transition hold time 7 t cldv data valid delay 49 t arych ardy resolution transition setup time 8 t chdx status hold time 50 t clarx ardy active hold time 9 t chlh ale active delay 51 t arychl ardy inactive holding time 10 t lhll ale width 52 t arylcl ardy setup time 11 t chll ale inactive delay 53 t invch peripheral setup time 12 t avll ad address valid to ale low 54 t invcl drq setup time 13 t llax ad address hold from ale inactive 55 t cltmv timer output delay 14 t avch ad address valid to clock high 57 t resin res setup time 15 t claz ad address float delay 58 t hvcl hold setup 16 t clcsv mcs /pcs active delay 59 t rhdx rd high to data hold on ad bus 17 t cxcsx mcs /pcs hold from command inactive 61 t lock maximum pll lock time 18 t chcsx mcs /pcs inactive delay 62 t clhav hlda valid delay 19 t dxdl den inactive to dt/r low 63 t chcz command lines float delay 20 t cvctv control active delay 1 64 t chcv command lines valid delay (after float) 21 t cvdex den inactive delay 65 t avwl a address valid to wr low 22 t chctv control active delay 2 66 t avrl a address valid to rd low 23 t lhav ale high to address valid 67 t chcsv clkouta high to lcs /ucs valid 24 t azrl ad address float to rd active 68 t chav clkouta high to address valid 25 t clrl rd active delay 69 t cicoa x1 to clkouta skew 26 t rlrh rd pulse width 70 t cicob x1 to clkoutb skew 27 t clrh rd inactive delay 71 t clev clkouta low to sden valid 28 t rhlh rd inactive to ale high 72 t clsl clkouta low to sclk low 29 t rhav rd inactive to ad address active 75 t dvsh data valid to sclk high 30 t cldox data hold time 77 t shdx sclk high to spi data hold 31 t cvctx control inactive delay 78 t sldv sclk low to spi data valid 32 t wlwh wr pulse width 79 t chrfd clkouta high to rfsh valid 33 t whlh wr inactive to ale high 80 t clclx lcs inactive delay 34 t whdx data hold after wr 81 t clcsl lcs active delay 35 t whdex wr inactive to den inactive 82 t clrf clkouta high to rfsh invalid 36 t ckin x1 period 83 t coaob clkouta to clkoutb skew 37 t clck x1 low time 84 t lrll lcs precharge pulse width 38 t chck x1 high time 85 t rfcy rfsh cycle time 39 t ckhl x1 fall time 86 t lcrf lcs inactive to rfsh active delay 40 t cklh x1 rise time 87 t avbl a address valid to whb , wlb low 42 t clcl clkouta period
am186/188em and am186/188emlv microcontrollers 63 preliminary switching characteristics over commercial operating range read cycle (20 mhz and 25 mhz) note: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , inta 1Cinta 0 , wr , whb , and wlb signals. c if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 10 10 ns 2 t cldx data in hold (c) 3 3 ns general timing responses 3 t chsv status active delay 0 25 0 20 ns 4 t clsh status inactive delay 0 25 0 20 ns 5 t clav ad address valid delay and bhe 0 25 0 20 ns 6 t clax address hold 0 25 0 20 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10= 30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 25 t clax =0 20 ns 16 t clcsv mcs /pcs active delay 0 25 0 20 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 25 0 20 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 25 0 20 ns 21 t cvdex den inactive delay 0 25 0 20 ns 22 t chctv control active delay 2 (b) 0 25 0 20 ns 23 t lhav ale high to address valid 20 15 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 25 0 20 ns 26 t rlrh rd pulse width 2t clcl C15=85 2t clcl C15= 65 ns 27 t clrh rd inactive delay 0 25 0 20 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 29 t rhav rd inactive to ad address active (a) t clcl C10=40 t clcl C10= 30 ns 59 t rhdx rd high to data hold on ad bus (c) 0 0 ns 66 t avrl a address valid to rd low (a) 2t clcl C15=85 2t clcl C15= 65 ns 67 t chcsv clkouta high to lcs /ucs valid 0 25 0 20 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns
64 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range read cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , inta 1Cinta 0 , wr , whb , and wlb signals. c if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 8 5 ns 2 t cldx data in hold (c) 3 2 ns general timing responses 3 t chsv status active delay 0 15 0 12 ns 4 t clsh status inactive delay 0 15 0 12 ns 5 t clav ad address valid delay and bhe 0 15 0 12 ns 6 t clax address hold 0 25 0 20 ns 7 t cldv data valid delay 0 15 0 12 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5 =20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address valid to ale low (a) t clch C2 t clch C2 ns 13 t llax ad address hold from ale inactive (a) t chcl C2 t chcl C2 ns 14 t avch ad address valid to clock high 0 0 ns 15 t claz ad address float delay t clax =0 15 t clax =0 12 ns 16 t clcsv mcs /pcs active delay 0 15 0 12 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch C2 t clch C2 ns 18 t chcsx mcs /pcs inactive delay 0 15 0 12 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 15 0 12 ns 21 t cvdex den inactive delay 0 15 0 12 ns 22 t chctv control active delay 2 (b) 0 15 0 12 ns 23 t lhav ale high to address valid 10 7.5 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 15 0 10 ns 26 t rlrh rd pulse width 2t clcl C15=45 2t clcl C10=40 ns 27 t clrh rd inactive delay 0 15 0 12 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C2 ns 29 t rhav rd inactive to ad address active (a) t clcl C10=20 t clcl C5 =20 ns 59 t rhdx rd high to data hold on ad bus (c) 0 0 ns 66 t avrl a address valid to rd low (a) 2t clcl C15=45 2t clcl C10=40 ns 67 t chcsv clkouta high to lcs /ucs valid 0 15 0 10 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns
am186/188em and am186/188emlv microcontrollers 65 preliminary read cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 lcs , ucs ad15Cad0*, ad7Cad0** rd mcs 1Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 address a19Ca0 den dt/r s6 bhe * ale 1 2 3 4 5 6 8 9 13 14 15 16 17 18 19 20 21 22 22 24 25 26 27 29 68 66 67 28 10 uzi s6 ao15Cao8** notes: * am186em microcontroller only ** am188em microcontroller only *** changes in t 4 phase of the clock preceding next bus cycle if followed by read, inta, or halt 59 23 11 s6 data status address address 12 bhe *** ***
66 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range write cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , inta 1Cinta 0 , wr , whb , and wlb signals. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 25 0 20 ns 4 t clsh status inactive delay 0 25 0 20 ns 5 t clav ad address valid delay and bhe 0 25 0 20 ns 6 t clax address hold 0 25 0 20 ns 7 t cldv data valid delay 0 25 0 20 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10= 40 t clcl C10= 30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address valid to ale low (a) t clch t clch ns 13 t llax ad address hold from ale inactive (a) t chcl t chcl ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 25 0 20 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch t clch ns 18 t chcsx mcs /pcs inactive delay 0 25 0 20 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 25 0 20 ns 22 t chctv control active delay 2 0 25 0 20 ns 23 t lhav ale high to address valid 20 15 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 25 0 20 ns 32 t wlwh wr pulse width 2t clcl C10 =90 2t clcl C10 =70 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10= 40 t clcl C10= 30 ns 35 t whdex wr inactive to den inactive (a) t clch C3 t clch C3 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C3 ns 67 t chcsv clkouta high to lcs /ucs valid 0 25 0 20 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns 87 t avbl a address valid to whb , wlb low t chcl C3 25 t chcl C3 20 ns
am186/188em and am186/188emlv microcontrollers 67 preliminary switching characteristics over commercial operating range write cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , inta 1Cinta 0 , wr , whb , and wlb signals. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 15 0 12 ns 4 t clsh status inactive delay 0 15 0 12 ns 5 t clav ad address valid delay and bhe 0 15 0 12 ns 6 t clax address hold 0 25 0 20 ns 7 t cldv data valid delay 0 15 0 12 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10= 20 t clcl C5 =20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address valid to ale low (a) t clch t clch ns 13 t llax ad address hold from ale inactive (a) t chcl t chcl ns 14 t avch ad address valid to clock high 0 0 ns 16 t clcsv mcs /pcs active delay 0 15 0 12 ns 17 t cxcsx mcs /pcs hold from command inactive (a) t clch t clch ns 18 t chcsx mcs /pcs inactive delay 0 15 0 12 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 15 0 12 ns 22 t chctv control active delay 2 0 15 0 12 ns 23 t lhav ale high to address valid 10 7.5 ns write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 15 0 12 ns 32 t wlwh wr pulse width 2t clcl C10 =50 2t clcl C10 =40 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10= 20 t clcl C10= 15 ns 35 t whdex wr inactive to den inactive (a) t clch C5 t clch ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C1.25 ns 67 t chcsv clkouta high to lcs /ucs valid 0 15 0 10 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns 87 t avbl a address valid to whb, wlb low t chcl C3 15 t chcl C1.25 12 ns
68 am186/188em and am186/188emlv microcontrollers preliminary write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 status lcs , ucs address data ad15Cad0*, ad7Cad0** wr mcs 3Cmcs 0, pcs 6Cpcs 5, pcs 3Cpcs 0 address a19Ca0 den dt/r s6 s6 ale whb *, wlb * wb ** bhe * 3 4 5 7 8 9 10 11 12 13 14 16 17 18 19 67 68 65 35 31 20 30 34 32 31 33 uzi s6 20 31 87 ao15Cao8** note: * am186em microcontroller only ** am188em microcontroller only *** changes in t 4 phase of the clock preceding next bus cycle if followed by read, inta, or halt. 23 address bhe 6 22 *** *** 22 20
am186/188em and am186/188emlv microcontrollers 69 preliminary switching characteristics over commercial operating range psram read cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 10 10 ns 2 t cldx data in hold (b) 3 3 ns general timing responses 5 t clav ad address valid delay and bhe 0 25 0 20 ns 7 t cldv data valid delay 0 25 0 20 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10= 40 t clcl C10= 30 ns 11 t chll ale inactive delay 25 20 ns 23 t lhav ale high to address valid 20 15 ns 80 t clclx lcs inactive delay 0 25 0 20 ns 81 t clcsl lcs active delay 0 25 0 20 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C3 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 25 0 20 ns 26 t rlrh rd pulse width 2t clcl C15 =85 2t clcl C15 =65 ns 27 t clrh rd inactive delay 0 25 0 20 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 59 t rhdx rd high to data hold on ad bus (b) 0 0 ns 66 t avrl a address valid to rd low 2t clcl C15 =85 2t clcl C15 =65 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns
70 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range psram read cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b if either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 8 5 ns 2 t cldx data in hold (b) 3 2 ns general timing responses 5 t clav ad address valid delay and bhe 0 15 0 12 ns 7 t cldv data valid delay 0 15 0 12 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10= 20 t clcl C5= 20 ns 11 t chll ale inactive delay 15 12 ns 23 t lhav ale high to address valid 10 7.5 ns 80 t clclx lcs inactive delay 0 15 0 12 ns 81 t clcsl lcs active delay 0 15 0 12 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C1.25 ns read cycle timing responses 24 t azrl ad address float to rd active 0 0 ns 25 t clrl rd active delay 0 15 0 10 ns 26 t rlrh rd pulse width 2t clcl C15 =45 2t clcl C10 =40 ns 27 t clrh rd inactive delay 0 15 0 12 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C1.25 ns 59 t rhdx rd high to data hold on ad bus (b) 0 0 ns 66 t avrl a address valid to rd low 2t clcl C15 =45 2t clcl C10 =40 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns
am186/188em and am186/188emlv microcontrollers 71 preliminary psram read cycle waveforms data clkouta t 1 t 2 t3 t w lcs address ad15Cad0*, ad7Cad0** rd address a19Ca0 s6 s6 ale 1 2 5 7 8 9 11 24 25 26 27 68 66 28 10 s6 t4 81 84 t 1 address 80 80 27 ao15Cao8** address notes: * am186em microcontroller only ** am188em microcontroller only 59 23
72 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range psram write cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , wr , whb , and wlb signals. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit general timing responses 5 t clav ad address valid delay and bhe 0 25 0 20 ns 7 t cldv data valid delay 0 25 0 20 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 23 t lhav ale high to address valid 20 15 ns 20 t cvctv control active delay 1 (b) 0 25 0 20 ns 80 t clclx lcs inactive delay 0 25 0 20 ns 81 t clcsl lcs active delay 0 25 0 20 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C 3 write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 25 0 20 ns 32 t wlwh wr pulse width 2t clcl C10 =90 2t clcl C10 =70 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=40 t clcl C10=30 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C3 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns 87 t avbl a address valid to whb , wlb low t chcl C3 25 t chcl C3 20 ns
am186/188em and am186/188emlv microcontrollers 73 preliminary switching characteristics over commercial operating range psram write cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den , wr , whb , and wlb signals. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit general timing responses 5 t clav ad address valid delay and bhe 0 15 0 12 ns 7 t cldv data valid delay 0 15 0 12 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 20 t cvctv control active delay 1 (b) 0 15 0 12 ns 23 t lhav ale high to address valid 10 7.5 ns 80 t clclx lcs inactive delay 0 15 0 12 ns 81 t clcsl lcs active delay 0 15 0 12 ns 84 t lrll lcs precharge pulse width t clcl + t clch C3 t clcl + t clch C1.25 write cycle timing responses 30 t cldox data hold time 0 0 ns 31 t cvctx control inactive delay (b) 0 15 0 12 ns 32 t wlwh wr pulse width 2t clcl C10 =50 2t clcl C10 =40 ns 33 t whlh wr inactive to ale high (a) t clch C2 t clch C2 ns 34 t whdx data hold after wr (a) t clcl C10=20 t clcl C10=15 ns 65 t avwl a address valid to wr low t clcl +t chcl C3 t clcl +t chcl C1.25 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns 87 t avbl a address valid to whb , wlb low t chcl C3 15 t chcl C1.25 12 ns
74 am186/188em and am186/188emlv microcontrollers preliminary psram write cycle waveforms clkouta t 1 t 2 t 3 t 4 t w lcs address data ad15Cad0*, ad7Cad0** wr address a19Ca0 s6 s6 ale whb *, wlb * wb ** 5 7 8 9 10 11 68 65 20 30 34 32 33 t 1 31 20 80 84 81 87 80 31 ao15Cao8** address notes: * am186em microcontroller only ** am188em microcontroller only 23 s6
am186/188em and am186/188emlv microcontrollers 75 preliminary switching characteristics over commercial operating range psram refresh cycle (20 mhz and 25 mhz) note: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit general timing responses 9 t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10= 40 t clcl C10= 30 ns 11 t chll ale inactive delay 25 20 ns read/write cycle timing responses 25 t clrl rd active delay 0 25 0 20 ns 26 t rlrh rd pulse width 2t clcl C15 =85 2t clcl C15 =65 ns 27 t clrh rd inactive delay 0 25 0 20 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C3 ns 80 t clclx lcs inactive delay 0 25 0 20 ns 81 t clcsl lcs active delay 0 25 0 20 ns refresh timing cycle parameters 79 t clrfd clkouta low to rfsh valid 0 25 0 20 ns 82 t clrf clkouta high to rfsh invalid 0 25 0 20 ns 85 t rfcy rfsh cycle time 6 t clcl 6 t clcl ns 86 t lcrf lcs inactive to rfsh active delay 2t clcl C3 2t clcl C3
76 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range psram refresh cycle (33 mhz and 40 mhz) note: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit general timing responses 9 t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5 =20 ns 11 t chll ale inactive delay 15 12 ns read/write cycle timing responses 25 t clrl rd active delay 0 15 0 10 ns 26 t rlrh rd pulse width 2t clcl C15 =45 2t clcl C10 =40 ns 27 t clrh rd inactive delay 0 15 0 12 ns 28 t rhlh rd inactive to ale high (a) t clch C3 t clch C2 ns 80 t clclx lcs inactive delay 0 15 0 12 ns 81 t clcsl lcs active delay 0 15 0 12 ns refresh timing cycle parameters 79 t clrfd clkouta low to rfsh valid 0 15 0 12 ns 82 t clrf clkouta high to rfsh invalid 0 15 0 12 ns 85 t rfcy rfsh cycle time 6 t clcl 6 t clcl ns 86 t lcrf lcs inactive to rfsh active delay 2t clcl C3 2t clcl C1.25
am186/188em and am186/188emlv microcontrollers 77 preliminary psram refresh cycle waveforms clkouta t 1 t 2 t 3 t 4 t w * lcs rd address a19Ca0 ale 9 25 26 27 28 10 rfsh 11 t 1 79 85 82 80 81 86 * the period tw is fixed at 3 wait states for psram auto refresh only. 27 note:
78 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range interrupt acknowledge cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt/r signals. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 10 10 ns 2 t cldx data in hold 3 3 ns general timing responses 3 t chsv status active delay 0 25 0 20 ns 4 t clsh status inactive delay 0 25 0 20 ns 7 t cldv data valid delay 0 25 0 20 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 12 t avll ad address invalid to ale low (a) t clch t clch ns 15 t claz ad address float delay t clax =0 25 t clax =0 20 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 25 0 20 ns 21 t cvdex den inactive delay 0 25 0 20 ns 22 t chctv control active delay 2 (c) 0 25 0 20 ns 23 t lhav ale high to address valid 20 15 ns 31 t cvctx control inactive delay (b) 0 25 0 20 ns 68 t chav clkouta high to a address valid 0 25 0 20 ns
am186/188em and am186/188emlv microcontrollers 79 preliminary switching characteristics over commercial operating range interrupt acknowledge cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the inta 1Cinta 0 signals. c this parameter applies to the den and dt/r signals. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit general timing requirements 1 t dvcl data in setup 8 5 ns 2 t cldx data in hold 3 2 ns general timing responses 3 t chsv status active delay 0 15 0 12 ns 4 t clsh status inactive delay 0 15 0 12 ns 7 t cldv data valid delay 0 15 0 12 ns 8 t chdx status hold time 0 0 ns 9 t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 12 t avll ad address invalid to ale low (a) t clch t clch ns 15 t claz ad address float delay t clax =0 15 t clax =0 12 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 20 t cvctv control active delay 1 (b) 0 15 0 12 ns 21 t cvdex den inactive delay 0 15 0 12 ns 22 t chctv control active delay 2 (c) 0 15 0 12 ns 23 t lhav ale high to address valid 10 7.5 ns 31 t cvctx control inactive delay (b) 0 15 0 12 ns 68 t chav clkouta high to a address valid 0 15 0 10 ns
80 am186/188em and am186/188emlv microcontrollers preliminary interrupt acknowledge cycle waveforms clkouta t 1 t 2 t 3 t 4 t w s 2Cs 0 status ale ad15Cad0*, ad7Cad0** inta 1Cinta 0 den dt/r ptr address a19Ca0 s6 s6 bhe * 8 1 2 3 4 7 9 10 11 12 15 19 20 22 22 22 68 31 (a) (b) (c) (d) s6 21 notes: * am186em microcontroller only ** am188em microcontroller only a the status bits become inactive in the state preceding t 4 . b the data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to t cldx (min). c this parameter applies for an interrupt acknowledge cycle that follows a write cycle. d if followed by a write cycle, this change occurs in the state preceding that write cycle. ao15Cao8** address 23 bhe
am186/188em and am186/188emlv microcontrollers 81 preliminary switching characteristics over commercial operating range software halt cycle (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den signal. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 25 0 20 ns 4 t clsh status inactive delay 0 25 0 20 ns 5 t clav ad address invalid delay and bhe 0 25 0 20 ns 9 t chlh ale active delay 25 20 ns 10 t lhll ale width t clcl C10=40 t clcl C10=30 ns 11 t chll ale inactive delay 25 20 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 22 t chctv control active delay 2 (b) 0 25 0 20 ns 68 t chav clkouta high to a address invalid 0 25 0 20 ns
82 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range software halt cycle (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a equal loading on referenced pins. b this parameter applies to the den signal. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit general timing responses 3 t chsv status active delay 0 15 0 12 ns 4 t clsh status inactive delay 0 15 0 12 ns 5 t clav ad address invalid delay and bhe 0 15 0 12 ns 9 t chlh ale active delay 15 12 ns 10 t lhll ale width t clcl C10=20 t clcl C5=20 ns 11 t chll ale inactive delay 15 12 ns 19 t dxdl den inactive to dt/r low (a) 0 0 ns 22 t chctv control active delay 2 (b) 0 15 0 12 ns 68 t chav clkouta high to a address invalid 0 15 0 10 ns
am186/188em and am186/188emlv microcontrollers 83 preliminary software halt cycle waveforms clkouta t 1 t 2 t i t i s 2Cs 0 status ale invalid address s6, ad15Cad0*, ad7Cad0**, ao15-ao8** den dt/r invalid address a19Ca0 3 4 5 9 10 11 19 22 68 notes: * am186em microcontroller only ** am188em microcontroller only
84 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range clock (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a the specifications for clkin are applicable to the normal pll and clkdiv2 modes. the pll should be used for operations from 16.667 mhz to 40 mhz. for operations below 16.667 mhz, the clkdiv2 mode should be used. because the clkdiv2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for clkdiv2 mode. for example, use the 20 mhz clkin specifications for 10 mhz operation. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit clkin requirements 36 t ckin x1 period (a) 50 60 40 60 ns 37 t clck x1 low time (1.5 v) (a) 15 15 ns 38 t chck x1 high time (1.5 v) (a) 15 15 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 5 ns clkout timing 42 t clcl clkouta period 50 40 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C2 =23 0.5t clcl C2 =18 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C2 =23 0.5t clcl C2 =18 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 3 3 ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 3 3 ns 61 t lock maximum pll lock time 1 1 ms 69 t cicoa x1 to clkouta skew 15 15 ns 70 t cicob x1 to clkoutb skew 21 21 ns
am186/188em and am186/188emlv microcontrollers 85 preliminary switching characteristics over commercial operating range clock (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a the specifications for clkin are applicable to the normal pll and clkdiv2 modes. the pll should be used for operations from 16.667 mhz to 40 mhz. for operations below 16.667 mhz, the clkdiv2 mode should be used. because the clkdiv2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for clkdiv2 mode. for example, use the 20 mhz clkin specifications for 10 mhz operation. preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit clkin requirements 36 t ckin x1 period (a) 30 60 25 60 ns 37 t clck x1 low time (1.5 v) (a) 10 7.5 ns 38 t chck x1 high time (1.5 v) (a) 10 7.5 ns 39 t ckhl x1 fall time (3.5 to 1.0 v) (a) 5 5 ns 40 t cklh x1 rise time (1.0 to 3.5 v) (a) 5 5 ns clkout timing 42 t clcl clkouta period 30 25 ns 43 t clch clkouta low time (c l =50 pf) 0.5t clcl C1.5 =13.5 0.5t clcl C1.25 =11.25 ns 44 t chcl clkouta high time (c l =50 pf) 0.5t clcl C1.5 =13.5 0.5t clcl C1.25 =11.25 ns 45 t ch1ch2 clkouta rise time (1.0 to 3.5 v) 3 3 ns 46 t cl2cl1 clkouta fall time (3.5 to 1.0 v) 3 3 ns 61 t lock maximum pll lock time 1 1 ms 69 t cicoa x1 to clkouta skew 15 15 ns 70 t cicob x1 to clkoutb skew 21 21 ns
86 am186/188em and am186/188emlv microcontrollers preliminary clock waveformsactive mode clock waveformspower-save mode x1 x2 clkoutb clkouta (active, f=000) 36 37 39 40 42 43 46 69 70 38 44 45 x1 clkouta (a) x2 clkoutb (c) clkoutb (b) notes: a the clock divisor select (f2Cf0) bits in the power save control register (pdcon) are set to 010 (divide by 4). b the clkoutb output frequency (cbf) bit in the power save control register (pdcon) is set to 1. c the clkoutb output frequency (cbf) bit in the power save control register (pdcon) is set to 0.
am186/188em and am186/188emlv microcontrollers 87 preliminary switching characteristics over commercial operating range ready and peripheral timing (20 mhz and 25 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. preliminary preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 10 10 ns 48 t clsry srdy transition hold time (a) 3 3 ns 49 t arych ardy resolution transition setup time (b) 10 10 ns 50 t clarx ardy active hold time (a) 4 4 ns 51 t arychl ardy inactive holding time 6 6 ns 52 t arylcl ardy setup time (a) 15 15 ns 53 t invch peripheral setup time (b) 10 10 ns 54 t invcl drq setup time (b) 10 10 ns peripheral timing responses 55 t cltmv timer output delay 25 20 ns
88 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range ready and peripheral timing (33 mhz and 40 mhz) notes: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a this timing must be met to guarantee proper operation. b this timing must be met to guarantee recognition at the clock edge. synchronous ready waveforms preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit ready and peripheral timing requirements 47 t srycl srdy transition setup time (a) 8 5 ns 48 t clsry srdy transition hold time (a) 3 2 ns 49 t arych ardy resolution transition setup time (b) 8 5 ns 50 t clarx ardy active hold time (a) 4 3 ns 51 t arychl ardy inactive holding time 6 5 ns 52 t arylcl ardy setup time (a) 10 5 ns 53 t invch peripheral setup time (b) 8 5 ns 54 t invcl drq setup time (b) 8 5 ns peripheral timing responses 55 t cltmv timer output delay 15 12 ns clkouta t w t w t w t 4 srdy t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 case 3 case 4 47 48 case 1
am186/188em and am186/188emlv microcontrollers 89 preliminary asynchronous ready waveforms peripheral waveforms clkouta t w t w t w t 4 ardy (normally not- ready system) t 3 t w t w t 4 t 2 t 3 t w t 4 t 1 t 2 t 3 t 4 case 2 case 3 case 4 ardy (normally ready system) 49 50 49 51 50 52 case 1 clkouta tmrout1C tmrout0 drq1Cdrq0 int4Cint0, nmi, tmrin1Ctmrin0 53 54 55
90 am186/188em and am186/188emlv microcontrollers preliminary switching characteristics over commercial operating range reset and bus hold (20 mhz and 25 mhz) note: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a this timing must be met to guarantee recognition at the next clock. reset and bus hold (33 mhz and 40 mhz) note: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. a this timing must be met to guarantee recognition at the next clock. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit reset and bus hold timing requirements 5 t clav ad address valid delay and bhe 0 25 0 20 ns 15 t claz ad address float delay 0 25 0 20 ns 57 t resin res setup time 10 10 ns 58 t hvcl hold setup (a) 10 10 ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 25 0 20 ns 63 t chcz command lines float delay 25 20 ns 64 t chcv command lines valid delay (after float) 25 20 ns preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit reset and bus hold timing requirements 5 t clav ad address valid delay and bhe 0 15 0 12 ns 15 t claz ad address float delay 0 15 0 12 ns 57 t resin res setup time 8 5 ns 58 t hvcl hold setup (a) 8 5 ns reset and bus hold timing responses 62 t clhav hlda valid delay 0 15 0 12 ns 63 t chcz command lines float delay 15 12 ns 64 t chcv command lines valid delay (after float) 15 12 ns
am186/188em and am186/188emlv microcontrollers 91 preliminary reset waveforms signals related to reset waveforms x1 res clkouta 57 57 res clkouta bhe /aden , rfsh 2/aden , s6/clkdiv 2, and uzi ad15Cad0 (186) ao15Cao8, ad7Cad0 (188) three-state three-state
92 am186/188em and am186/188emlv microcontrollers preliminary bus hold waveformsentering bus hold waveformsleaving clkouta t i t i t i ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2Cs 0 whb , wlb hold t 4 t i t i case 2 58 62 15 63 case 1 clkouta t i t i t 1 ad15Cad0, den hlda a19Ca0, s6, rd , wr , bhe , dt/r , s 2Cs 0 whb , wlb hold t i t 4 t 1 case 2 t i t i 58 62 64 5 case 1
am186/188em and am186/188emlv microcontrollers 93 preliminary switching characteristics over commercial operating range synchronous serial interface (ssi) (20 mhz and 25 mhz) note: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. synchronous serial interface (ssi) (33 mhz and 40 mhz) note: all timing parameters are measured at 1.5 v with 50 pf loading on clkouta unless otherwise noted. all output test conditions are with c l = 50 pf. for switching tests, v il = 0.45 v and v ih = 2.4 v, except at x1 where v ih = v cc C 0.5 v. preliminary parameter 20 mhz 25 mhz no. symbol description min max min max unit synchronous serial port timing requirements 75 t dvsh data valid to sclk high 10 10 ns 77 t shdx sclk high to spi data hold 3 3 ns synchronous serial port timing responses 71 t clev clkouta low to sden valid 25 20 ns 72 t clsl clkouta low to sclk low 25 20 ns 78 t sldv sclk low to data valid 25 20 ns preliminary parameter 33 mhz 40 mhz no. symbol description min max min max unit synchronous serial port timing requirements 75 t dvsh data valid to sclk high 8 5 ns 77 t shdx sclk high to spi data hold 2 2 ns synchronous serial port timing responses 71 t clev clkouta low to sden valid 0 15 0 12 ns 72 t clsl clkouta low to sclk low 0 15 0 12 ns 78 t sldv sclk low to data valid 0 15 0 12 ns
94 am186/188em and am186/188emlv microcontrollers preliminary synchronous serial interface (ssi) waveforms note: sdata is bidirectional and used for either transmit (tx) or receive (rx). timing is shown separately for each case. clkouta sdata (rx) sclk sden data 72 78 71 75 77 sdata (tx) data 72
am186/188em and am186/188emlv microcontrollers 95 preliminary tqfp physical dimensions pql 100, trimmed and formed thin quad flat pack pin 100 pin 25 pin 1 id 12.00 ref notes: 1. all measurements are in millimeters unless otherwise noted. 2. not to scale; for reference only. pql100 4-15-94 C b C C a C C d C pin 75 12.00 ref 13.80 14.20 15.80 16.20 pin 50 13.80 14.20 15.80 16.20 C a C C c C s s1.60 max 0.50 basic 1.00 ref 1.35 1.45 see detail x seating plane top view side view
96 am186/188em and am186/188emlv microcontrollers preliminary pql 100 (continued) 0.17 0.27 0.05 0.15 seating plane detail x 0.17 0.27 0 C 7 gage plane 0.20 0.45 0.75 0.13 0.20 0 min 0.25 0.14 0.18 section s-s 1.60 max notes: 1. all measurements are in millimeters unless otherwise noted. 2. not to scale; for reference only. max 0.08 lead coplanarity r pql100 4-15-94
am186/188em and am186/188emlv microcontrollers 97 preliminary pqfp physical dimensions pqr 100, trimmed and formed plastic quad flat pack notes: 1. all measurements are in millimeters unless otherwise noted. 2. not to scale; for reference only. 17.00 17.40 13.90 14.10 12.35 ref pin 80 pin 100 pin 30 pin 50 pin 1 i.d. 19.90 20.10 see detail x seating 0.65 basic 0.25 min 2.70 2.90 3.35 max s s - C a C - C d C C b C C a C C c C top view side view 18.85 ref 23.00 23.40 pqr100 4-15-94
98 am186/188em and am186/188emlv microcontrollers preliminary pqfp pqr 100 (continued) 0.20 min. flat shoulder 7 typ. 0 min. 0.30 0.05 r gage plane 0.25 0.73 1.03 0 C 7 7 typ. detail x 0.22 0.38 0.15 0.23 3.35 max section s-s 0.15 0.23 0.22 0.38 note: not to scale; for reference only. pqr100 4-15-94 trademarks amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am386 and am486 are registered trademarks of advanced micro devices, inc. am186, am188, e86, k86, lan, and amd facts-on-demand are trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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